AT89LP51 Atmel Corporation, AT89LP51 Datasheet - Page 63

• Manufacturer Part Number: AT89LP51
• Manufacturer: Atmel Corporation

Specifications of AT89LP51

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

14.5
14.5.1
3709D–MICRO–12/11
More About Mode 0
Two-Wire (Half-Duplex) Mode
The Broadcast Address for each slave is created by taking the logic OR of SADDR and SADEN.
Zeros in this result are trended as don’t cares. In most cases, interpreting the don’t cares as
ones, the broadcast address will be FF hexadecimal.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are loaded with
“0”s. This produces a given address of all “don’t cares” as well as a Broadcast address of all
“don’t cares”. This effectively disables the Automatic Addressing mode and allows the microcon-
troller to use standard 80C51-type UART drivers which do not make use of this feature.
In Mode 0, the UART is configured as either a two wire half-duplex or three wire full-duplex syn-
chronous serial interface. In two-wire mode serial data enters and exits through RXD and TXD
outputs the shift clock. In three-wire mode serial data enters through MISO, exits through MOSI
and SCK outputs the shift clock. Eight data bits are transmitted/received, with the LSB first.
ure 14-3
Mode 0 and associated timing. The baud rate is programmable to 1/2 or 1/4 the system fre-
quency by setting/clearing the SMOD1 bit in Fast mode, or 1/3 or 1/6 the system frequency in
Compatibility mode. However, changing SMOD1 has an effect on the relationship between the
clock and data as described below. The baud rate can also be generated by Timer 1 by setting
TB8.
Table 14-4.
Transmission is initiated by any instruction that uses SBUF as a destination register. The “write
to SBUF” signal also loads a “1” into the 9th position of the transmit shift register and tells the TX
Control Block to begin a transmission. The internal timing is such that one full bit slot may elapse
between “write to SBUF” and activation of SEND.
SEND transfers the output of the shift register to the alternate output function line of P3.0, and
also transfers Shift Clock to the alternate output function line of P3.1. As data bits shift out to the
right, “0”s come in from the left. When the MSB of the data byte is at the output position of the
shift register, the “1” that was initially loaded into the 9th position is just to the left of the MSB,
and all positions to the left of that contain “0”s. This condition flags the TX Control block to do
one last shift, then deactivate SEND and set TI.
Reception is initiated by the condition REN = 1 and RI = 0. At the next clock cycle, the RX Con-
trol unit writes the bits 11111110B to the receive shift register and activates RECEIVE in the
next clock phase. RECEIVE enables Shift Clock to the alternate output function line of P3.1. As
data bits come in from the right, “1”s shift out to the left. When the “0” that was initially loaded
into the right-most position arrives at the left-most position in the shift register, it flags the RX
Control block to do one last shift and load SBUF. Then RECEIVE is cleared and RI is set.
The relationship between the shift clock and data is determined by the combination of the SM2
and SMOD1 bits as listed in
TB8
0
0
1
1
Table 14-4
and
SMOD1
Figure 14-5 on page 67
Mode 0 Baud Rates
0
1
0
1
lists the baud rate options for Mode 0.
(Timer 1 Overflow) / 4
(Timer 1 Overflow) / 2
Baud Rate (Fast)
Table 14-5
f
f
SYS
SYS
/4
/2
show simplified functional diagrams of the serial port in
and shown in
Figure
Baud Rate (Compatibility)
(Timer 1 Overflow) / 4
(Timer 1 Overflow) / 2
. The SM2 bit determines the idle
f
f
SYS
SYS
/6
/3
AT89LP51/52
Fig-
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