AT89LS51 Atmel Corporation, AT89LS51 Datasheet
AT89LS51
Specifications of AT89LS51
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AT89LS51 Summary of contents
Page 1
... RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89LS51 is designed with static logic for opera- tion down to zero frequency and supports two software selectable power saving modes ...
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... GND 20 21 2.2 44-lead TQFP (MOSI) P1.5 1 (MISO) P1.6 2 (SCK) P1.7 3 RST 4 (RXD) P3 (TXD) P3.1 7 (INT0) P3.2 8 (INT1) P3.3 9 (T0) P3.4 10 (T1) P3.5 11 AT89LS51 2 2.3 44-lead PLCC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) 33 P0.4 (AD4) 32 P0.5 (AD5) 31 P0.6 (AD6 ...
Page 3
... P0.0 - P0.7 PORT 0 DRIVERS PORT 0 RAM LATCH ACC TMP2 TMP1 ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW WATCH PORT 3 DOG LATCH PORT 3 DRIVERS P3.0 - P3.7 AT89LS51 P2.0 - P2.7 PORT 2 DRIVERS PORT 2 FLASH LATCH PROGRAM STACK ADDRESS POINTER REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DUAL DPTR PROGRAM PORT 1 ...
Page 4
... Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program- ming and verification. AT89LS51 4 ) because of the internal pull-ups. IL Alternate Functions ...
Page 5
... As inputs, Port 3 pins that are externally being pulled low will source current (I Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89LS51, as shown in the following table. Port Pin P3 ...
Page 6
... Note that not all of the addresses are occupied, and unoccupied addresses may not be imple- mented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. AT89LS51 6 for internal program executions during Flash programming. ...
Page 7
... Table 5-1. AT89LS51 SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC 0E0H 00000000 0D8H PSW 0D0H 00000000 0C8H 0C0H IP 0B8H XX000000 P3 0B0H 11111111 IE 0A8H 0X000000 P2 0A0H 11111111 SCON SBUF 98H 00000000 XXXXXXXX P1 90H 11111111 TCON TMOD 88H 00000000 00000000 P0 SP ...
Page 8
... Data Pointer Register. Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset. AT89LS51 8 AUXR: Auxiliary Register Address = 8EH – ...
Page 9
... Data Memory The AT89LS51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space. 7. Watchdog Timer (One-time Enabled with Reset-out) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets ...
Page 10
... UART operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 9. Timer 0 and 1 Timer 0 and Timer 1 in the AT89LS51 operate the same way as Timer 0 and Timer 1 in the AT89C51. For further information on the timers’ operation, please click on the document link below: http://www ...
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... Interrupts The AT89LS51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in Figure Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once ...
Page 12
... XTAL1 is driven, as shown in requirements on the duty cycle of the external clock signal, since the input to the internal clock- ing circuitry is hrough a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Figure 11-1. Oscillator Connections Note: AT89LS51 12 0 INT0 1 TF0 ...
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... SIGNAL is restored to its normal operating level and must be held active long enough to allow CC Status of External Pins During Idle and Power-down Modes Program Memory ALE Internal 1 External 1 Internal 0 External 0 AT89LS51 XTAL2 XTAL1 GND PSEN PORT0 PORT1 PORT2 1 Data Data Data 1 Float Data ...
Page 14
... Program Memory Lock Bits The AT89LS51 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in Table 14- When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. ...
Page 15
... With a 16 MHz oscillator clock, the maximum SCK frequency is 1 MHz. 16.1 Serial Programming Algorithm To program and verify the AT89LS51 in the serial programming mode, the following sequence is recommended: 1. Power-up sequence: a. Apply power between VCC and GND pins. b. Set RST pin to “H”. ...
Page 16
... Notes: 1. Each PROG pulse is 200 ns - 500 ns for Chip Erase. 2. Each PROG pulse is 200 ns - 500 ns for Write Code Data. 3. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits. 4. RDY/BSY signal is output on P3.0 during programming don’t care. AT89LS51 16 power off. CC ALE/ EA/ ...
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... MHz P3.0 XTAL1 RST GND PSEN AT89S51 ADDR. P1.0-P1.7 CC 0000H/FFFH P0 P2 A11 P2.6 P2.7 ALE SEE FLASH P3.3 PROGRAMMING MODES TABLE P3.6 P3.7 XTAL MHz XTAL1 RST GND PSEN AT89LS51 4.5V - 5.5V PGM DATA PROG RDY/ BSY V IH 4.5V - 5.5V PGM DATA (USE 10K PULLUPS ...
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... Data Float After ENABLE EHQZ t PROG High to BUSY Low GHBL t Byte Write Cycle Time WC Figure 18-1. Flash Programming and Verification Waveforms – Parallel Mode P1.0 - P1.7 P2.0 - P2.3 PORT 0 ALE/PROG EA/V PP P2.7 (ENABLE) P3.0 (RDY/BSY) AT89LS51 18 PP PROGRAMMING ADDRESS DATA DVGL GHDX t t AVGL GHAX t t SHGL GHSL t ...
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... Figure 18-2. Flash Memory Serial Downloading 19. Flash Programming and Verification Waveforms – Serial Mode Figure 19-1. Serial Programming Waveforms 3053C–MICRO–6/08 AT89LS51 INSTRUCTION P1.5/MOSI INPUT P1.6/MISO DATA OUTPUT P1.7/SCK CLOCK IN XTAL2 MHz XTAL1 GND AT89LS51 RST ...
Page 20
... For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready to be decoded. AT89LS51 20 Instruction Format ...
Page 21
... SCK t SHSL = -40⋅ 85⋅ Min 3 62 CLCL 8 t CLCL t CLCL 2 t CLCL 10 *NOTICE: AT89LS51 t SLSH t SLIV = 2.7V - 4.0V (Unless Otherwise Noted) CC Typ Max 500 400 CLCL Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device ...
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... Ports Maximum total I for all output pins exceeds the test condition than the listed test conditions. 2. Minimum V for Power-down is 2V. CC AT89LS51 22 = -40°C to 85°C and Condition (Except EA) (Except XTAL1, RST) (XTAL1, RST) (Ports I = 0.8 mA ...
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... CLCL 122 4t -130 CLCL 13 t -50 CLCL 287 7t -150 CLCL 13 t -50 CLCL 0 23 103 t -40 CLCL AT89LS51 Max Units 16 MHz -100 ns CLCL -105 ns CLCL ns t -25 ns CLCL ns 5t -105 ns CLCL ...
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... External Program Memory Read Cycle ALE PSEN PORT 0 PORT 2 25. External Data Memory Read Cycle ALE PSEN FROM RI OR DPL PORT 0 PORT 2 AT89LS51 24 t LHLL t t AVLL LLIV t LLPL t PLIV t PLAZ t LLAX t PXIX INSTR IN t AVIV A8 - A15 t LHLL t LLDV ...
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... QVWX AVLL t QVWH FROM RI OR DPL DATA OUT t AVWL P2 A15 FROM DPH t t CHCX CLCH CLCX Min 0 62 AT89LS51 t WHLH t WHQX FROM PCL INSTR A15 FROM PCH t CHCX t CHCL t CLCL Max Units 16 MHz ...
Page 26
... IL (1) 32. Float Waveforms Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V AT89LS51 26 = 2.7V to 4.0V and Load Capacitance = 80 pF MHz Osc Min 1.0 ...
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... Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 3053C–MICRO–6/08 Package 44A 44J 40P6 Package Type AT89LS51 Operation Range Industrial (-40° 85° ...
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... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89LS51 TITLE 44A, 44-lead Body Size, 1 ...
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... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3053C–MICRO–6/08 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) AT89LS51 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4 ...
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... SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89LS51 30 D PIN 0º ~ 15º REF ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...