AT89S8253 Atmel Corporation, AT89S8253 Datasheet - Page 23

• Manufacturer Part Number: AT89S8253
• Manufacturer: Atmel Corporation

Specifications of AT89S8253

• Flash (kbytes): 12 Kbytes
• Max. Operating Frequency: 24 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 2048
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

Notes:
14. Serial Peripheral Interface
3286P–MICRO–3/10
1. SMOD0 is located at PCON.6.
2. f
osc
= oscillator frequency.
The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the
AT89S8253 and peripheral devices or between multiple AT89S8253 devices. The AT89S8253
SPI features include the following:
The interconnection between master and slave CPUs with SPI is shown in
pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock
(SCK), and Slave Select (SS). The SCK pin is the clock output in master mode, but is the clock
input in slave mode. The MSTR bit in SPCR determines the directions of MISO and MOSI. Also
notice that MOSI connects to MOSI and MISO to MISO. In master mode, SS/P1.4 is ignored and
may be used as a general-purpose input or output. In slave mode, SS must be driven low to
select an individual device as a slave. When SS is driven high, the slave’s SPI port is deacti-
vated and the MOSI/P1.5 pin can be used as a general-purpose input.
Figure 14-1. SPI Master-Slave Interconnection
• Full-Duplex, 3-Wire Synchronous Data Transfer
• Master or Slave Operation
• Maximum Bit Frequency = f/4 (f/2 if in x2 Clock Mode)
• LSB First or MSB First Data Transfer
• Four Programmable Bit Rates in Master Mode
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Double-Buffered Receive
• Double-Buffered Transmit (Enhanced Mode only)
• Wakeup from Idle Mode (Slave Mode only)
CLOCK GENERATOR
SPI
MSB
8-BIT SHIFT REGISTER
MASTER
LSB
MISO
MOSI MOSI
SCK
SS
V
CC
MISO
SCK
SS
MSB
8-BIT SHIFT REGISTER
AT89S8253
Figure
SLAVE
14-1. The four
LSB
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