ATmega324P Atmel Corporation, ATmega324P Datasheet - Page 171
ATmega324P
Manufacturer Part Number
ATmega324P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega324P
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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16. USART
16.1
16.2
16.3
8011O–AVR–07/10
Features
USART1 and USART0
Overview
•
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•
•
•
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The ATmega164P/324P/644P has two USART’s, USART0 and USART1.
The functionality for all USART’s is described below, most register and bit references in this sec-
tion are written in general form. A lower case “n” replaces the USART number.
USART0 and USART1 have different I/O registers as shown in
413.
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device.
A simplified block diagram of the USART Transmitter is shown in
accessible I/O Registers and I/O pins are shown in bold.
The Power Reducion USART0 bit, PRUSART0, in
48
The Power Reducion USART1 bit, PRUSART1, in
48
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
must be disabled by writing a logical zero to it.
must be disabled by writing a logical zero to it.
ATmega164P/324P/644P
”PRR – Power Reduction Register” on page
”PRR – Power Reduction Register” on page
Figure 16-1 on page
”Register Summary” on page
172. CPU
171
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