ATmega3250 Atmel Corporation, ATmega3250 Datasheet - Page 56
ATmega3250
Manufacturer Part Number
ATmega3250
Description
Manufacturer
Atmel Corporation
Specifications of ATmega3250
Flash (kbytes)
32 Kbytes
Pin Count
100
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
25
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.2
13.2.1
2570N–AVR–05/11
Register Description
EICRA – External Interrupt Control Register A
Figure 13-1. Pin Change Interrupt
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 13-1.
Bit
(0x69)
Read/Write
Initial Value
ISC01
0
0
1
1
pcint_setflag
pcint_in_(n)
PCINT(n)
pcint_syn
pin_sync
ISC00
pin_lat
Interrupt 0 Sense Control
PCINT(0)
PCIF
R
7
–
0
0
1
0
1
clk
clk
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
LE
R
6
–
0
Table
pin_lat
D
13-1. The value on the INT0 pin is sampled before detecting
R
5
–
0
Q
pin_sync
PCINT(0) in PCMSK(x)
4
–
R
0
ATmega325/3250/645/6450
pcint_in_(0)
R
3
–
0
0
x
clk
R
2
–
0
pcint_syn
ISC01
R/W
1
0
pcint_setflag
ISC00
R/W
0
0
EICRA
PCIF
56
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