ATmega325P Atmel Corporation, ATmega325P Datasheet

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ATmega325P

Manufacturer Part Number
ATmega325P
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega325P

Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Features
High Performance, Low Power AVR
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Speed Grade:
Temperature range:
Ultra-Low Power Consumption
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-Chip 2-cycle Multiplier
– 32K Bytes of In-System Self-programmable Flash program memory
– 1K Bytes EEPROM
– 2K Bytes Internal SRAM
– Write/Erase cyles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Programming Lock for Software Security
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
– 54/69 Programmable I/O Lines
– 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP
– ATmega325PV/ATmega3250PV:
– ATmega325P/3250P:
– -40°C to 85°C Industrial
– Active Mode:
– Power-down Mode:
– Power-save Mode:
Mode
Standby
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
420 µA at 1 MHz, 1.8V
40 nA at 1.8V
750 nA at 1.8V
®
8-Bit Microcontroller
(1)
8-bit
Microcontroller
with 32K Bytes
In-System
Programmable
Flash
ATmega325P/V
ATmega3250P/V
Preliminary
8023FS–AVR–07/09

ATmega325P Summary of contents

Page 1

... Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby • I/O and Packages – 54/69 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP • Speed Grade: – ATmega325PV/ATmega3250PV MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATmega325P/3250P MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Temperature range: – -40°C to 85°C Industrial • ...

Page 2

... Pin Configurations Figure 1-1. ATmega325P/3250P 2 Pinout ATmega3250P DNC 1 2 (RXD/PCINT0) PE0 INDEX CORNER (TXD/PCINT1) PE1 3 4 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 5 6 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 7 8 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 9 10 VCC GND 11 12 DNC (PCINT24) PJ0 13 14 (PCINT25) PJ1 DNC 15 16 ...

Page 3

... Overview The ATmega325P/3250P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega325P/3250P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...

Page 4

... Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. ATmega325P/3250P 4 PF0 - PF7 PA0 - PA7 ...

Page 5

... Self-Programmable Flash on a monolithic chip, the Atmel ATmega325P/3250P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded con- trol applications. The ATmega325P/3250P AVR is supported with a full suite of program and system develop- ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. ...

Page 6

... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega325P/3250P as listed on page 2.3.5 Port C (PC7 ...

Page 7

... The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega325P/3250P as listed on page 2.3.8 Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit) ...

Page 8

... AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con- nected to V through a low-pass filter. 2.3.16 AREF This is the analog reference pin for the A/D Converter. ATmega325P/3250P 8 308. Shorter pulses are not guaranteed to generate a reset. , even if the ADC is not used. If the ADC is used, it should be connected ”System and Reset CC 8023FS– ...

Page 9

... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 8023FS–AVR–07/09 ATmega325P/3250P 9 ...

Page 10

... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega325P/3250P 10 1. ...

Page 11

... USART0 Data Register ATmega325P/3250P Bit 3 Bit 2 Bit ...

Page 12

... Reserved - (0x8E) Reserved - (0x8D) Reserved - (0x8C) OCR1BH (0x8B) OCR1BL (0x8A) OCR1AH (0x89) OCR1AL (0x88) ICR1H (0x87) ICR1L (0x86) ATmega325P/3250P 343 Bit 6 Bit 5 Bit 4 Bit 3 USART0 Baud Rate Register Low - - - UMSEL0 UPM01 UPM00 USBS0 TXCIE0 UDRIE0 RXEN0 TXEN0 TXC0 UDRE0 FE0 DOR0 ...

Page 13

... OCDR6 OCDR5 OCDR4 ACBG ACO ACI - - - SPI Data Register WCOL - - SPE DORD MSTR General Purpose I/O Register General Purpose I/O Register - - - - - - Timer/Counter0 Output Compare A ATmega325P/3250P Bit 3 Bit 2 Bit WGM12 CS12 CS11 - - WGM11 - - AIN1D ADC3D ADC2D ADC1D - - - MUX3 MUX2 MUX1 - ADTS2 ADTS1 ...

Page 14

... When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega325P/3250P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...

Page 15

... V= 0) then PC ← ⊕ then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← ATmega325P/3250P Operation Flags #Clocks Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S ...

Page 16

... Rd, Z+ Load Program Memory and Post-Inc SPM Store Program Memory IN Rd Port OUT P, Rr Out Port ATmega325P/3250P 347 Description then PC ← then PC ← then PC ← I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Rd(7)← ...

Page 17

... Sleep WDR Watchdog Reset BREAK Break 8023FS–AVR–07/09 Description STACK ← ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only ATmega325P/3250P Operation Flags #Clocks None None None None None None ...

Page 18

... Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) ATmega325P/3250P 349 (2) Ordering Code Package Type ATmega325PV-10AU ATmega325PV-10MU ATmega325P-20AU ATmega325P-20MU and Figure 26-2 on page 306. Package Type (1) Operational Range 64A Industrial 0⋅ ...

Page 19

... Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 8023FS–AVR–07/09 (2) Ordering Code Package Type ATmega3250PV-10AU ATmega3250P-20AU and Figure 26-2 on page 306. Package Type ATmega325P/3250P (1) Operational Range Industrial 100A 0⋅C to 85⋅C) (-4 Industrial 100A 0⋅C to 85⋅C) (-4 ...

Page 20

... JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATmega325P/3250P 351 B PIN 1 IDENTIFIER ...

Page 21

... Option A Triangle 2 3 Option B Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 64M1, 64-pad 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) ATmega325P/3250P C SEATING PLANE A1 A 0.08 C SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM NOTE A ...

Page 22

... This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATmega325P/3250P 353 B PIN 1 IDENTIFIER ...

Page 23

... Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 32.3 ATmega325P rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer. 1. Interrupts may be lost when writing the timer registers in the asynchronous timer. ...

Page 24

... Timer/Counter register (TCNTx) is 0x00. Problem Fix/Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). ATmega325P/3250P 355 8023FS–AVR–07/09 ...

Page 25

... Port A Data Register” on page Bullet five updated in ”Asynchronous Operation of Timer/Counter2” on page Updated ”System and Reset Characterizations” on page Added Errata for ”ATmega325P rev. C” on page 354 page 355. Added ”Data Retention” on page 10. Updated Device and JTAG ID in ” ...

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