ATmega328P Atmel Corporation, ATmega328P Datasheet - Page 146
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ATmega328P
Manufacturer Part Number
ATmega328P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega328P
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
18.1
18.2
8271D–AVR–05/11
Features
Overview
•
•
•
•
•
•
•
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified
block diagram of the 8-bit Timer/Counter is shown in
I/O pins, refer to
I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register
and bit locations are listed in the
The PRTIM2 bit in
enable Timer/Counter2 module.
Figure 18-1. 8-bit Timer/Counter Block Diagram
Single Channel Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)
Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock
”Pinout ATmega48A/PA/88A/PA/168A/PA/328/P” on page
”Minimizing Power Consumption” on page 43
ATmega48A/PA/88A/PA/168A/PA/328/P
Timer/Counter
TCCRnA
OCRnA
TCNTn
OCRnB
=
=
”Register Description” on page
Direction
Count
Clear
Control Logic
TOP
=
TCCRnB
Value
BOTTOM
Fixed
TOP
clk
=
Tn
0
Figure
18-1. For the actual placement of
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TOVn
(Int.Req.)
Clock Select
160.
Generation
Generation
Waveform
Waveform
( From Prescaler )
Detector
Edge
must be written to zero to
2. CPU accessible
OCnA
OCnB
Tn
146
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