ATmega329A Atmel Corporation, ATmega329A Datasheet - Page 110

• Manufacturer Part Number: ATmega329A
• Manufacturer: Atmel Corporation

Specifications of ATmega329A

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.9.2
8284D–AVR–6/11
TCNT0 – Timer/Counter Register
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
Note:
Table 15-5
rect PWM mode.
Table 15-5.
Note:
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 15-6.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a compare match between TCNT0 and the OCR0A Register.
Bit
0x26 (0x46)
Read/Write
Initial Value
CS02
COM0A1
0
0
0
0
1
1
1
1
0
0
1
1
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
CS01
pare match is ignored, but the set or clear is done at BOTTOM. See
page 104
pare match is ignored, but the set or clear is done at TOP. See
page 105
shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase cor-
0
0
1
1
0
0
1
1
Compare Output Mode, Phase Correct PWM Mode
Clock Select Bit Description
R/W
COM0A0
7
0
CS00
for more details.
for more details.
0
1
0
1
0
1
0
1
0
1
0
1
R/W
6
0
Description
No clock source (Timer/Counter stopped)
clk
clk
clk
clk
clk
External clock source on T0 pin. Clock on falling edge.
External clock source on T0 pin. Clock on rising edge.
Description
Normal port operation, OC0A disconnected.
Reserved
Clear OC0A on compare match when up-counting. Set OC0A on
compare match when down counting.
Set OC0A on compare match when up-counting. Clear OC0A on
compare match when down counting.
I/O
I/O
I/O
I/O
I/O
/(No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
R/W
5
0
R/W
4
0
TCNT0[7:0]
R/W
3
0
R/W
2
0
(1)
”Phase Correct PWM Mode” on
R/W
1
0
”Fast PWM Mode” on
R/W
0
0
TCNT0
110