ATmega32M1 Automotive Atmel Corporation, ATmega32M1 Automotive Datasheet - Page 9
ATmega32M1 Automotive
Manufacturer Part Number
ATmega32M1 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATMEGA16M1_AUTOMOTIVE.pdf
(12 pages)
3.ATMEGA16M1_AUTOMOTIVE.pdf
(25 pages)
4.ATMEGA16M1_AUTOMOTIVE.pdf
(367 pages)
Specifications of ATmega32M1 Automotive
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #2
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #3
- ATMEGA16M1_AUTOMOTIVE PDF datasheet #4
- Current page: 9 of 225
- Download datasheet (4Mb)
5.4.1
7701E–AVR–02/11
SREG – AVR Status Register
The Status Register is not automatically stored when entering an interrupt routine and
restored when returning from an interrupt. This must be handled by software.
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the global interrupt
enable register is cleared, none of the interrupts are enabled independently of the individual
interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and
is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and
cleared by the application with the SEI and CLI instructions, as described in the instruction set
summary.
• Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the register file can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the register file by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. Half carry is useful in
BCD arithmetic. See the instruction set reference for detailed information.
• Bit 4 – S: Sign Bit, S = N
The S-bit is always an exclusive OR between the negative flag N and the two's complement
overflow flag V. See the "Instruction Set Description" for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two's complement overflow flag V supports two's complement arithmetic. See the instruc-
tion set summary for detailed information.
• Bit 2 – N: Negative Flag
The negative flag N indicates a negative result in an arithmetic or logic operation. See the
instruction set summary for detailed information.
• Bit 1 – Z: Zero Flag
The zero flag Z indicates a zero result in an arithmetic or logic operation. See the instruction
set summary for detailed information.
• Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the instruction set
summary for detailed information.
Bit
0x3F (0x5F)
Read/Write
Initial Value
R/W
7
0
I
R/W
T
6
0
Atmel ATtiny24/44/84 [Preliminary]
V
R/W
H
5
0
R/W
S
4
0
R/W
3
V
0
R/W
N
2
0
R/W
1
Z
0
R/W
C
0
0
SREG
9
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