ATmega48P Atmel Corporation, ATmega48P Datasheet
ATmega48P
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ATmega48P Summary of contents
Page 1
... • Speed Grade: – ATmega48P/88P/168PV 4MHz @ 1.8 - 5.5V 10MHz @ 2.7 - 5.5V – ATmega48P/88P/168P 10MHz @ 2.7 - 5.5V 20MHz @ 4.5 - 5.5V • Low Power Consumption at 1MHz, 1.8V, 25°C: – Active Mode: 0.3mA – Power-down Mode: 0.1µA – Power-save Mode: 0.8µA (Including 32kHz RTC) Note: 1. See ”Data Retention” on page 8 ® ...
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... Pin Configurations Figure 1-1. Pinout ATmega48P/88P/168P TQFP Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6 (PCINT6/XTAL1/TOSC1) PB6 7 (PCINT7/XTAL2/TOSC2) PB7 8 28 MLF Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 VCC 3 GND 4 (PCINT6/XTAL1/TOSC1) PB6 5 (PCINT7/XTAL2/TOSC2) PB7 6 (PCINT21/OC0B/T1) PD5 7 NOTE: Bottom pad should be soldered to ground. ...
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... The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. 8025M–AVR–6/11 ”System Clock and Clock Options” on page Table 29-3 on page ATmega48P/88P/168P ”Alternate Functions of Port B” on page 27. 314. Shorter pulses are not guaran- ”Alternate Functions of Port C” on page ...
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... These pins are powered from the analog supply and serve as 10-bit ADC channels. 2. Overview The ATmega48P/88P/168P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48P/88P/168P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed ...
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... T/C 0 8bit T/C 2 USART 0 PORT D (8) 8025M–AVR–6/11 Power Timer Supervision POR / BOD & RESET Flash Clock 16bit T/C 1 Analog Comp. SPI PORT B (8) PD[0..7] PB[0..7] ATmega48P/88P/168P debugWIRE PROGRAM LOGIC SRAM CPU AVCC AREF GND 2 A/D Conv. Internal 6 Bandgap TWI PORT C (7) RESET XTAL[1..2] PC[0..6] ADC[6..7] ...
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... Atmel ATmega48P/88P/168P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega48P/88P/168P AVR is supported with a full suite of program and system develop- ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. ...
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... ATmega88P and ATmega168P support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega48P, there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash. ...
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... API’s to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide ATmega48P/88P/168P 8 1. ® ® ...
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... This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- 8025M–AVR–6/11 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega48P/88P/168P Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog ...
Page 10
... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega48P/88P/168P has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 8025M–AVR–6/ R/W R/W R/W R ⊕ V ATmega48P/88P/168P R/W R/W R/W R SREG 11 ...
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... Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. ATmega48P/88P/168P 12 shows the structure of the 32 general purpose working registers in the CPU. ...
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... Data is pushed onto the stack Return address is pushed onto the stack with a subroutine call or Decremented by 2 interrupt Incremented by 1 Data is popped from the stack Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt ATmega48P/88P/168P Figure 7- R26 (0x1A ...
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... Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Execute Figure 7-5 operation using two register operands is executed, and the result is stored back to the destina- tion register. Figure 7-5. Register Operands Fetch ALU Operation Execute ATmega48P/88P/168P SP15 SP14 SP13 SP7 SP6 ...
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... CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. 8025M–AVR–6/11 for details. ”Interrupts” on page 58 ”Boot Loader Support – Read-While-Write Self-Programming, 275. ATmega48P/88P/168P ”Memory Program- ”Interrupts” on page 58. The list also for more information. 15 ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATmega48P/88P/168P 16 ; store SREG value ; disable interrupts during timed sequence ...
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... The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega48P/88P/168P Program Counter (PC) is 11/12/13 bits wide, thus addressing the 2/4/8 program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in on page 267 and ATmega168P” ...
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... Figure 8-1. Figure 8-2. ATmega48P/88P/168P 18 Program Memory Map, ATmega48P Program Memory Application Flash Section Program Memory Map, ATmega88P and ATmega168P Program Memory Application Flash Section Boot Flash Section 0x0000 0x7FF 0x0000 0x0FFF/0x1FFF 8025M–AVR–6/11 ...
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... SRAM Data Memory Figure 8-3 The ATmega48P/88P/168P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... Figure 8-4. 8.4 EEPROM Data Memory The ATmega48P/88P/168P contains 256/512/512 bytes of data EEPROM memory orga- nized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... I/O Memory The I/O space definition of the ATmega48P/88P/168P is shown in 395. All ATmega48P/88P/168P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these regis- ters, the value of single bits can be checked by using the SBIS and SBIC instructions ...
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... Initial Value • Bits 7:6 – Reserved These bits are reserved bits in the ATmega48P/88P/168P and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be trig- gered when writing EEPE ...
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... EEPROM access to fail recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. 8025M–AVR–6/11 EEPROM Mode Bits Programming EEPM0 Time Operation 0 3.4 ms Erase and Write in one operation (Atomic Operation) 1 1.8 ms Erase Only 0 1.8 ms Write Only 1 – Reserved for future use ATmega48P/88P/168P ”Boot Loader 23 ...
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... The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. ATmega48P/88P/168P 24 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles ...
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... EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret /* Wait for completion of previous write */ while(EECR & (1<<EEPE Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); ATmega48P/88P/168P 25 ...
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... GPIOR2 – General Purpose I/O Register 2 Bit 0x2B (0x4B) Read/Write Initial Value 8.6.5 GPIOR1 – General Purpose I/O Register 1 Bit 0x2A (0x4A) Read/Write Initial Value 8.6.6 GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write Initial Value ATmega48P/88P/168P 26 r16,EEDR ; MSB R/W R/W R/W R MSB ...
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... AVR Clock I/O Control Unit clk ASY System Clock Prescaler Clock Multiplexer Timer/Counter External Clock Oscillator is halted, TWI address recognition in all sleep modes. I/O ATmega48P/88P/168P CPU Core RAM clk ADC clk CPU clk FLASH Reset Logic Watchdog Timer Source clock Watchdog clock Watchdog ...
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... To ensure sufficient V the device reset is released by all other reset sources. describes the start conditions for the internal reset. The delay (t Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The ATmega48P/88P/168P 28 ASY Device Clocking Options Select 1. For all fuses “ ...
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... Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( 4 before it releases the reset, and the time-out delay CC 31. Table 9-3 on page ATmega48P/88P/168P 322. = 3.0V) Number of Cycles CC 0 512 8K (8,192) Figure 9-2 on page 30. Either a quartz 30. For ceramic resonators, the capacitor val- . The ” ...
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... Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power ATmega48P/88P/168P 30 Crystal Oscillator Connections C2 C1 30. Low Power Crystal Oscillator Operating Modes (1) Recommended Range for (MHz) Capacitors C1 and C2 (pF) ...
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... Recommended Range for Capacitors C1 and C2 (pF) 0 MHz frequency exceeds the specification of the device (depends on V can be programmed in order to divide the internal frequency must be ensured that the resulting divided clock meets the frequency specification of the device. ATmega48P/88P/168P Additional Delay from Reset (V = 5.0V) CKSEL0 ...
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... Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: ATmega48P/88P/168P 32 Crystal Oscillator Connections C2 C1 Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save ...
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... The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals, load capasitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor. ATmega48P/88P/168P oscillator is optimized for very low power consumption, and thus when selecting crystals, see 9.0 pF and 12.5 pF crystals Table 9-7 ...
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... When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 9-12 on page Table 9-12. Power Conditions BOD enabled Fast rising power Slowly rising power Note: ATmega48P/88P/168P 34 Start-up Times for the Low-frequency Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save ( 32K CK 1 ...
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... To run the device on an external clock, the CKSEL Fuses must be programmed Table 9-15). Crystal Oscillator Clock Frequency Frequency MHz External Clock Drive Configuration NC EXTERNAL CLOCK SIGNAL ATmega48P/88P/168P Table 9-13. CKSEL[3:0] 0011 Additional Delay from Reset (1) 14CK 14CK + 4 ms 14CK + 64 ms CKSEL[3:0] ...
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... System Clock Prescaler The ATmega48P/88P/168P has a system clock prescaler, and the system clock can be divided by setting the decrease the system clock frequency and the power consumption when the requirement for pro- cessing power is low ...
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... Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bitsin CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 8025M–AVR–6/11 ATmega48P/88P/168P 37 ...
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... These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchro- nous peripherals is reduced when a division factor is used. The division factors are given in Table 9-17 on page ATmega48P/88P/168P ...
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... ATmega48P/88P/168P CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 39 ...
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... SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. ATmega48P/88P/168P 40 for more details. presents the different clock systems in the ATmega48P/88P/168P, and Oscillators ( ...
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... CPU FLASH 1. Timer/Counter2 will only keep running in asynchronous mode, see PWM and Asynchronous Operation” on page 142 ATmega48P/88P/168P Table 28-6 on page level has dropped during the sleep period. CC 45. Writing this bit to one turns off the BOD in rele- ...
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... SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. ATmega48P/88P/168P 42 ”External Interrupts” on page 68 ”Clock Sources” on page 28. 8025M– ...
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... Reference” on page 50 8025M–AVR–6/11 ”PRR – Power Reduction Register” on page ”Analog Comparator” on page 244 for details on the start-up time. ATmega48P/88P/168P ”Analog-to-Digital Converter” on page 248 for details on how to configure the Analog ”Brown-out Detection” on page 49 ”Internal Volt- ...
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... If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the main clock source is enabled and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption. ATmega48P/88P/168P 44 ”Watchdog Timer” on page 51 for details on how to configure the Watchdog Timer ...
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... Read/Write Initial Value • Bits 7:4 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero. • Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 10-2. ...
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... Bit 4 – Res: Reserved bit This bit is reserved in ATmega48P/88P/168P and will always read as zero. • Bit 3 – PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. • ...
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... Reset Vector. For the ATmega168P, the instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. For the ATmega48P and ATmega88P, the instruction placed at the Reset Vector must be an RJMP – Relative Jump – ...
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... A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V CC Figure 11-2. MCU Start-up, RESET Tied to V TIME-OUT INTERNAL ATmega48P/88P/168P 48 Power-on Reset Circuit Brown-out Reset Circuit Pull-up Resistor SPIKE ...
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... RSTDISBL fuse, see Figure 11-4. External Reset During Operation 11.5 Brown-out Detection ATmega48P/88P/168P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD CC can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection ...
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... Figure 11-6. Watchdog System Reset During Operation 11.7 Internal Voltage Reference ATmega48P/88P/168P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 11.7.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in reference is not always turned on ...
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... Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 11.8.2 Overview ATmega48P/88P/168P has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached ...
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... WDCE bit cleared. This must be done in one operation. The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. ATmega48P/88P/168P 52 8025M–AVR–6/11 ...
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... Turn on global interrupt sei ret (1) __disable_interrupt(); __watchdog_reset(); /* Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); 1. See ”About Code Examples” on page 8. ATmega48P/88P/168P 53 ...
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... Note: Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period. ATmega48P/88P/168P 54 (1) r16, (1<<WDCE) | (1<<WDE) Got four cycles to set the new values from here - r16, (1< ...
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... Initial Value • Bit 7:4 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero. • Bit 3 – WDRF: Watchdog System Reset Flag This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...
Page 56
... The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown in Table 11-2 on page Table 11-2. WDP3 ATmega48P/88P/168P 56 Watchdog Timer Configuration (1) WDE WDIE Mode 0 0 Stopped 0 1 Interrupt Mode ...
Page 57
... Watchdog Timer Prescale Select (Continued) Number of WDT Oscillator WDP2 WDP1 WDP0 512K (524288) cycles 1024K (1048576) cycles ATmega48P/88P/168P Typical Time-out at Cycles V = 5.0V CC 4.0 s 8.0 s Reserved 57 ...
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... Each Interrupt Vector occupies two instruction words in ATmega168P, and one instruction word in ATmega48P and ATmega88P. • ATmega48P does not have a separate Boot Loader Section. In ATmega88P and ATmega168P, the Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is affected by the IVSEL bit in MCUCR. ...
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... Table 12-1. Reset and Interrupt Vectors in ATmega48P (Continued) Vector No. Program Address 24 0x017 25 0x018 26 0x019 The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega48P is: Address Labels Code 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0x008 0x009 ...
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... Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. ATmega48P/88P/168P 60 Interrupt Definition External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset ...
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... Main program start out SPH,r16 ldi r16, low(RAMEND) out SPL,r16 sei <instr> xxx ATmega48P/88P/168P (1) Interrupt Vectors Start Address 0x001 Boot Reset Address + 0x001 0x001 Boot Reset Address + 0x001 Table 27-7 on page 287. For the BOOTRST Fuse “1” Comments ; Reset Handler ...
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... MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88P is: Address Labels Code ; .org 0xC00 0xC00 0xC01 0xC02 ... 0xC19 ; 0xC1A ATmega48P/88P/168P 62 RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> ...
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... USART, UDRE USART, Data Register Empty USART, TX USART, Tx Complete ADC ADC Conversion Complete EE READY EEPROM Ready ANALOG COMP Analog Comparator TWI 2-wire Serial Interface SPM READY Store Program Memory Ready ATmega48P/88P/168P ; Set Stack Pointer to top of RAM ; Enable interrupts ”Boot Loader Sup- 275. 63 ...
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... ATmega48P/88P/168P 64 shows reset and Interrupt Vectors placement for the various combina- Reset and Interrupt Vectors Placement in ATmega168P IVSEL Reset Address 0 0x000 1 0x000 0 Boot Reset Address 1 Boot Reset Address 1. The Boot Reset Address is shown in means unprogrammed while “ ...
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... RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx ATmega48P/88P/168P ; Set Stack Pointer to top of RAM ; Enable interrupts Comments ; Set Stack Pointer to top of RAM ; Enable interrupts ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler ; IRQ0 Handler ...
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... IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: This bit is not available in ATmega48P. ATmega48P/88P/168P 66 jmp ...
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... IVSEL description above. See Code Example below. Assembly Code Example Move_interrupts: C Code Example void Move_interrupts(void This bit is not available in ATmega48P. 8025M–AVR–6/11 ; Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) ...
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... The start-up time is defined by the SUT and CKSEL Fuses as described in ”System Clock and Clock Options” on page 13.1 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 13-1. Timing of pin change interrupts ATmega48P/88P/168P 68 27. Low level interrupt on INT0 and INT1 is detected asynchro- 27. pin_lat pcint_in_(0) PCINT(0) ...
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... Initial Value • Bit 7:4 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero. • Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre- sponding interrupt mask are set ...
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... Initial Value • Bit 7:2 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero. • Bit 1 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled ...
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... Initial Value • Bit 7:3 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero. • Bit 2 – PCIE2: Pin Change Interrupt Enable 2 When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is enabled ...
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... Read/Write Initial Value • Bit 7 – Reserved Bit This bit is an unused bit in the ATmega48P/88P/168P, and will always read as zero. • Bit 6:0 – PCINT[14:8]: Pin Change Enable Mask 14..8 Each PCINT[14:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[14:8] is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin ...
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... Ground as indicated in CC for a complete list of parameters. Pxn C pin ”Register Description” on page 78. Refer to the individual module sections for a full description of the alter- ATmega48P/88P/168P Figure 14-1. Refer to ”Electrical Char Logic See Figure "General Digital I/O" for Details 90. ” ...
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... If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. ATmega48P/88P/168P 74 (1) Pxn ...
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... Input 1 1 Input 0 X Output 1 X Output Figure 14-2, the PINxn Register bit and the preceding latch con- pd,max ATmega48P/88P/168P Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 14-3 shows a timing dia- and t respectively ...
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... The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. ATmega48P/88P/168P 76 SYSTEM CLK ...
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... Figure 14-2, the digital input signal can be clamped to ground at the input of the ”Alternate Port Functions” on page ATmega48P/88P/168P /2. CC 78. 77 ...
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... Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: ATmega48P/88P/168P 78 or GND is not recommended, since this may cause excessive currents if the pin is CC (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 ...
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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally. ATmega48P/88P/168P Fig- 79 ...
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... Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. TOSC1: Timer Oscillator pin 1. Used only if internal calibrated RC Oscillator is selected as chip clock source, and the asynchronous timer is enabled by the correct setting in ASSR. When the ATmega48P/88P/168P 80 Port B Pins Alternate Functions ...
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... PCINT2: Pin Change Interrupt source 2. The PB2 pin can serve as an external interrupt source. • OC1A/PCINT1 – Port B, Bit 1 OC1A, Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter1 Compare Match A. The PB1 pin has to be configured as an output (DDB1 set 8025M–AVR–6/11 ATmega48P/88P/168P 81 ...
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... PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Notes: ATmega48P/88P/168P 82 and Table 14-5 on page 83 relate the alternate functions of Port B to the overriding Figure 14-5 on page 78. SPI MSTR INPUT and SPI SLAVE OUTPUT consti- Overriding Signals for Alternate Functions in PB7..PB4 PB7/XTAL2/ PB6/XTAL1/ (1) ...
Page 83
... ADC3 (ADC Input Channel 3) PC3 PCINT11 (Pin Change Interrupt 11) ADC2 (ADC Input Channel 2) PC2 PCINT10 (Pin Change Interrupt 10) ADC1 (ADC Input Channel 1) PC1 PCINT9 (Pin Change Interrupt 9) ADC0 (ADC Input Channel 0) PC0 PCINT8 (Pin Change Interrupt 8) ATmega48P/88P/168P PB1/OC1A/ PB0/ICP1/ PCINT1 PCINT0 ...
Page 84
... PCINT11: Pin Change Interrupt source 11. The PC3 pin can serve as an external interrupt source. • ADC2/PCINT10 – Port C, Bit 2 PC2 can also be used as ADC input Channel 2. Note that ADC input channel 2 uses analog power. PCINT10: Pin Change Interrupt source 10. The PC2 pin can serve as an external interrupt source. ATmega48P/88P/168P 84 8025M–AVR–6/11 ...
Page 85
... When enabled, the 2-wire Serial Interface enables slew-rate controls on the output pins PC4 and PC5. This is not shown in the figure. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. ATmega48P/88P/168P (1) PC4/SDA/ADC4/PCINT12 TWEN PORTC4 • ...
Page 86
... DIEOE DIEOV DI AIO 14.3.3 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 14-9. Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 ATmega48P/88P/168P 86 Overriding Signals for Alternate Functions in PC3..PC0 PC3/ADC3/ PC2/ADC2/ PCINT11 PCINT10 ...
Page 87
... Timer/Counter0 Compare Match B. The PD3 pin has to be configured as an output (DDD3 set (one)) to serve this function. The OC2B pin is also the output pin for the PWM mode timer function. PCINT19: Pin Change Interrupt source 19. The PD3 pin can serve as an external interrupt source. 8025M–AVR–6/11 ATmega48P/88P/168P 87 ...
Page 88
... Table 14-10 shown in Table 14-10. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega48P/88P/168P 88 and Table 14-11 relate the alternate functions of Port D to the overriding signals Figure 14-5 on page 78. PD7/AIN1 PD6/AIN0/ /PCINT23 OC0A/PCINT22 ...
Page 89
... OC2B ENABLE 0 OC2B 0 INT1 ENABLE + INT0 ENABLE + PCINT19 • PCIE2 PCINT18 • PCIE1 1 1 PCINT19 INPUT PCINT18 INPUT INT1 INPUT INT0 INPUT – – ATmega48P/88P/168P PD1/TXD/ PD0/RXD/ PCINT17 PCINT16 TXEN RXEN 0 PORTD0 • PUD TXEN RXEN 1 0 TXEN 0 TXD 0 PCINT17 • PCIE2 PCINT16 • ...
Page 90
... Bit 0x08 (0x28) Read/Write Initial Value 14.4.6 DDRC – The Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 14.4.7 PINC – The Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial Value ATmega48P/88P/168P – BODS BODSE PUD R ...
Page 91
... R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R PIND7 PIND6 PIND5 PIND4 N/A N/A N/A N/A ATmega48P/88P/168P PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R/W R DDD3 DDD2 DDD1 DDD0 R/W R/W R/W R PIND3 PIND2 PIND1 PIND0 ...
Page 92
... Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM0 bit in enable Timer/Counter0 module. ATmega48P/88P/168P 92 ”Pinout ATmega48P/88P/168P” on page ”Register Description” on page ”Minimizing Power Consumption” on page 43 Figure 15-1. For the actual 2. CPU accessible I/O 104 ...
Page 93
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is depen- dent on the mode of operation. ATmega48P/88P/168P TOVn (Int.Req.) Clock Select ...
Page 94
... Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk count operations. ATmega48P/88P/168P 94 See Section “16.7.3” on page 121. ”Timer/Counter0 and Timer/Counter1 Prescalers” on page DATA BUS ...
Page 95
... PWM pulses, thereby making the output glitch-free. 8025M–AVR–6/11 97. (”Modes of Operation” on page shows a block diagram of the Output Compare unit. DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega48P/88P/168P 97). TCNTn OCFnx (Int.Req.) OCnx COMnx1:0 ”Modes of 95 ...
Page 96
... Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin system reset occur, the OC0x Register is reset to “0”. ATmega48P/88P/168P 96 Figure 15-4 shows a simplified ...
Page 97
... COMnx1 Waveform COMnx0 D Generator FOCn D PORT D clk I/O See Section “15.9” on page 104. Table 15-2 on page 96.). ”Timer/Counter Timing Diagrams” on page ATmega48P/88P/168P Q 1 OCnx Pin OCnx DDR 104. For fast PWM mode, refer to Table 15-4 on page 105. Table 15-3 on 102. 97 ...
Page 98
... For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for ATmega48P/88P/168P 98 Figure ...
Page 99
... OCnx Figure 15-6. The TCNT0 value is in the timing diagram shown as a his ATmega48P/88P/168P ) OCRnx OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 OC0 99 ...
Page 100
... Figure the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. ATmega48P/88P/168P 100 Table 15-6 on page 105). The actual OC0x value will only be visible on f OCnxPWM 15-7 ...
Page 101
... Compare Match. The point of this transition is to guarantee symmetry around BOT- TOM. There are two cases that give a transition without Compare Match. • OCRnx changes its value from MAX, like in OCn pin value is the same as the result of a down-counting Compare Match. To ensure 8025M–AVR–6/11 ATmega48P/88P/168P Table 15-7 on page 106) ...
Page 102
... Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk I/O TCNTn TOVn Figure 15-10 mode and PWM mode, where OCR0A is TOP. ATmega48P/88P/168P 102 Figure 15-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) MAX - 1 shows the same timing data, but with the prescaler enabled. ...
Page 103
... TCNTn (CTC) OCRnx OCFnx 8025M–AVR–6/11 I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 ATmega48P/88P/168P OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP /8) clk_I/O OCRnx + 2 BOTTOM + 1 103 ...
Page 104
... WGM02:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 15-2. COM0A1 Table 15-3 mode. Table 15-3. COM0A1 Note: ATmega48P/88P/168P 104 COM0A1 COM0A0 COM0B1 R/W R/W R Table 15-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits Compare Output Mode, non-PWM Mode ...
Page 105
... A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See for more details. ATmega48P/88P/168P (1) ”Phase Correct PWM Mode” on (1) ”Fast PWM Mode” on page 99 ...
Page 106
... Note: • Bits 3, 2 – Reserved These bits are reserved bits in the ATmega48P/88P/168P and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- ...
Page 107
... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Reserved These bits are reserved bits in the ATmega48P/88P/168P and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. 8025M– ...
Page 108
... Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0B pin. ATmega48P/88P/168P 108 Clock Select Bit Description CS01 CS00 Description ...
Page 109
... Initial Value • Bits 7:3 – Reserved These bits are reserved bits in the ATmega48P/88P/168P and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...
Page 110
... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page ATmega48P/88P/168P 110 Table 106. ...
Page 111
... Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM1 bit in enable Timer/Counter1 module. 8025M–AVR–6/11 ”Pinout ATmega48P/88P/168P” on page ”Register Description” on page ”PRR – Power Reduction Register” on page 46 ATmega48P/88P/168P Figure 16-1 ...
Page 112
... The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Coun- ter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See ATmega48P/88P/168P 112 Count Clear ...
Page 113
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation. ATmega48P/88P/168P 113 ...
Page 114
... The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. ATmega48P/88P/168P 114 (1) (1) 1. See ” ...
Page 115
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega48P/88P/168P 115 ...
Page 116
... The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and prescaler, see ATmega48P/88P/168P 116 (1) (1) 1. See ” ...
Page 117
... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear ”Modes of Operation” on page ATmega48P/88P/168P TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 123 ...
Page 118
... When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera- ATmega48P/88P/168P 118 DATA BUS TEMP (8-bit) ...
Page 119
... Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be 8025M–AVR–6/11 113. ATmega48P/88P/168P ”Accessing 16-bit Registers” (Figure 17-1 on page 139). The edge detector is also ...
Page 120
... For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Com- pare Register to either TOP or BOTTOM of the counting sequence. The synchronization ATmega48P/88P/168P 120 (See Section “16.9” on page shows a block diagram of the Output Compare unit. The small “ ...
Page 121
... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 8025M–AVR–6/11 113. ATmega48P/88P/168P ”Accessing 16-bit Registers” 121 ...
Page 122
... The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the Waveform Generator that no action on the OC1x Register performed on the next compare match. For compare output actions in the ATmega48P/88P/168P 122 Waveform ...
Page 123
... The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. 8025M–AVR–6/11 ATmega48P/88P/168P Table 16-1 on page 132. For fast PWM mode refer to 122.) ”Timer/Counter Timing Diagrams” on page ...
Page 124
... PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capaci- tors), hence reduces total system cost. ATmega48P/88P/168P 124 1 2 ...
Page 125
... The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location 8025M–AVR–6/11 ( log TOP R = ---------------------------------- - FPWM log ATmega48P/88P/168P ) Figure 16-7. The figure OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...
Page 126
... However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to ATmega48P/88P/168P 126 Table on page f ...
Page 127
... TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Reg- ister. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This 8025M–AVR–6/11 ATmega48P/88P/168P ( ) log ...
Page 128
... OCR1x Register is updated by the OCR1x Buffer Register, (see 8 and Figure The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and ATmega48P/88P/168P 128 f OCnxPCPWM 16-9). Table on page ...
Page 129
... R = ---------------------------------- - PFCPWM Figure 16-9. The figure shows phase and frequency correct shows the output generated is, in contrast to the phase correct mode, symmetri- ATmega48P/88P/168P ( ) + 1 TOP log OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set ...
Page 130
... The figures include information on when Interrupt Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling (clk TCNTn OCRnx OCFnx Figure 16-11 ATmega48P/88P/168P 130 f OCnxPFCPWM Figure 16-10 clk I/O clk Tn ...
Page 131
... TOP in various modes. When using phase and clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) ATmega48P/88P/168P OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 BOTTOM + 1 TOP - 2 131 ...
Page 132
... When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen- dent of the WGM13:0 bits setting. WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). Table 16-1. COM1A1/COM1B1 ATmega48P/88P/168P 132 shows the same timing data, but with the prescaler enabled. clk I/O ...
Page 133
... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. Section “16.9.4” on page 126. for more details. Table 16-4. Modes of operation supported by the Timer/Counter ATmega48P/88P/168P (1) Description Normal port operation, OC1A/OC1B disconnected. WGM13 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). ...
Page 134
... When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. ATmega48P/88P/168P 134 (1) WGM10 ...
Page 135
... I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge FOC1A FOC1B – R/W R ATmega48P/88P/168P – – – – Figure 0 – TCCR1C R 0 ...
Page 136
... The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. ATmega48P/88P/168P 136 7 6 ...
Page 137
... Initial Value • Bit 7, 6 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “ ...
Page 138
... Initial Value • Bit 7, 6 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13 used as the TOP value, the ICF1 Flag is set when the coun- ter reaches the TOP value ...
Page 139
... The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk clk I/O Synchronization ATmega48P/88P/168P and ”16-bit Timer/Counter1 with PWM” on page /8, f /64, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative Edge Detector ...
Page 140
... Oscillator source (crystal, resonator, and capacitors) tolerances recommended that maximum frequency of an external clock source is less than f An external clock source can not be prescaled. Figure 17-2. Prescaler for Timer/Counter0 and Timer/Counter1 PSRSYNC Note: ATmega48P/88P/168P 140 < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O ...
Page 141
... TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 8025M–AVR–6/ TSM – – – R ATmega48P/88P/168P – – PSRASY PSRSYNC R R R/W R GTCCR 141 ...
Page 142
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the The PRTIM2 bit in enable Timer/Counter2 module. Figure 18-1. 8-bit Timer/Counter Block Diagram ATmega48P/88P/168P 142 ”Pinout ATmega48P/88P/168P” on page ”Register Description” on page ”Minimizing Power Consumption” on page 43 Count Clear Control Logic Direction ...
Page 143
... MCU clock, clk T2 154. shows a block diagram of the counter and its surrounding environment. ATmega48P/88P/168P for details. The compare match event will also set the 162. For details on clock sources and prescaler, see . When the AS2 I/O ” ...
Page 144
... WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation Figure 18-3 ATmega48P/88P/168P 144 DATA BUS count clear ...
Page 145
... OCR2x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. 8025M–AVR–6/11 DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega48P/88P/168P TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 145 ...
Page 146
... The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2x state before the out- put is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of operation. ATmega48P/88P/168P 146 Waveform D ...
Page 147
... The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. 8025M–AVR–6/11 ATmega48P/88P/168P Table 18-5 on page 157. For fast PWM mode, refer to Table 18-7 on page 146.). ...
Page 148
... PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. ATmega48P/88P/168P 148 1 2 ...
Page 149
... The TCNT2 value is in the timing diagram shown as a his Table 18-3 on page ----------------- - OCnxPWM N 256 ATmega48P/88P/168P OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 156). The actual OC2x value will only clk_I/O ⋅ 149 ...
Page 150
... Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM ATmega48P/88P/168P 150 18-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating when OCR2A is set to zero ...
Page 151
... OCnxPCPWM Figure 18-7 contains timing data for basic Timer/Counter operation. The figure shows the I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega48P/88P/168P Table 18-4 on page 157). The actual OC2x f clk_I/O = ----------------- - ⋅ N 510 OCnx has a transition from high to low even though Figure 18-7 ...
Page 152
... TCNTn OCRnx OCFnx Figure 18-11 Figure 18-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk TCNTn (CTC) OCRnx OCFnx ATmega48P/88P/168P 152 I/O Tn /8) I/O MAX - 1 shows the setting of OCF2A in all modes except CTC mode. I/O Tn /8) I/O OCRnx - 1 OCRnx shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. ...
Page 153
... The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. 8025M–AVR–6/11 Enable interrupts, if needed. ATmega48P/88P/168P 153 ...
Page 154
... Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 18.10 Timer/Counter Prescaler Figure 18-12. Prescaler for Timer/Counter2 TOSC1 PSRASY The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter ATmega48P/88P/168P 154 clk clk I/O T2S Clear AS2 CS20 ...
Page 155
... T2S Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a predictable prescaler. 8025M–AVR–6/11 /256, and clk /1024. Additionally, clk T2S T2S ATmega48P/88P/168P /8, clk /32, clk T2S T2S as well as 0 (stop) may be selected. T2S /64, T2S ...
Page 156
... WGM22:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 18-2. COM2A1 Table 18-3 mode. Table 18-3. COM2A1 Note: ATmega48P/88P/168P 156 COM2A1 COM2A0 COM2B1 R/W R/W R Table 18-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits Compare Output Mode, non-PWM Mode ...
Page 157
... COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM Compare Output Mode, Fast PWM Mode COM2B0 Description 0 Normal port operation, OC2B disconnected. 1 Reserved Clear OC2B on Compare Match, set OC2B at BOTTOM, 0 (non-inverting mode). Set OC2B on Compare Match, clear OC2B at BOTTOM, 1 (inverting mode). ATmega48P/88P/168P (1) ”Phase Correct PWM Mode” on (1) 157 ...
Page 158
... Note: • Bits 3, 2 – Reserved These bits are reserved bits in the ATmega48P/88P/168P and will always read as zero. • Bits 1:0 – WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- ...
Page 159
... OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Reserved These bits are reserved bits in the ATmega48P/88P/168P and will always read as zero. • Bit 3 – WGM22: Waveform Generation Mode See the description in the • Bit 2:0 – CS22:0: Clock Select ...
Page 160
... Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2B pin. ATmega48P/88P/168P 160 Clock Select Bit Description CS21 CS20 Description ...
Page 161
... – – – – ATmega48P/88P/168P – OCIE2B OCIE2A TOIE2 R R/W R/W R – OCF2B OCF2A TOV2 R R/W R/W R TIMSK2 ...
Page 162
... A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value write is performed to any of the five Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. ATmega48P/88P/168P 162 7 6 ...
Page 163
... TSM bit is set. Refer to the description of the chronization Mode” on page 141 8025M–AVR–6/ TSM – – – R for a description of the Timer/Counter Synchronization mode. ATmega48P/88P/168P – – PSRASY PSRSYNC R R R/W R ”Bit 7 – TSM: Timer/Counter Syn- GTCCR 163 ...
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... Double Speed (CK/2) Master SPI Mode 19.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega48P/88P/168P and peripheral devices or between several AVR devices. The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 202. The PRSPI bit in module. ...
Page 165
... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low periods: Longer than 2 CPU clock cycles. High periods: Longer than 2 CPU clock cycles. 8025M–AVR–6/11 ATmega48P/88P/168P Figure 19-2 on page SHIFT ENABLE 165 ...
Page 166
... Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. ATmega48P/88P/168P 166 Table 19-1 on page 166. For more details on automatic port overrides, refer to 78 ...
Page 167
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See ”About Code Examples” on page 8. ATmega48P/88P/168P 167 ...
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... DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return Data Register */ return SPDR; } Note: ATmega48P/88P/168P 168 (1) r17,(1<<DD_MISO) DDR_SPI,r17 r17,(1<<SPE) SPCR,r17 r16,SPDR ( See ”About Code Examples” on page 8. 8025M–AVR–6/11 ...
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... Table 19-3 on page 171 and Table 19-4 on page SPI Modes Conditions 0 CPOL=0, CPHA=0 1 CPOL=0, CPHA=1 2 CPOL=1, CPHA=0 3 CPOL=1, CPHA=1 ATmega48P/88P/168P 171, as done in Table 19-2. Leading Edge Trailing eDge Sample (Rising) Setup (Falling) Setup (Rising) Sample (Falling) Sample (Falling) Setup (Rising) Setup (Falling) Sample (Rising) ...
Page 170
... Figure 19-3. SPI Transfer Format with CPHA = 0 Figure 19-4. SPI Transfer Format with CPHA = 1 ATmega48P/88P/168P 170 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 Bit 5 LSB first (DORD = 1) LSB Bit 1 Bit 2 SCK (CPOL = 0) ...
Page 171
... Figure 19-3 and Figure 19-4 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 19-3 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup ATmega48P/88P/168P CPOL CPHA SPR1 SPR0 R/W R/W R/W R for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 19-4 for an example ...
Page 172
... SPI Data Register. • Bit 5:1 – Reserved These bits are reserved bits in the ATmega48P/88P/168P and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods ...
Page 173
... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 8025M–AVR–6/ MSB R/W R/W R/W R ATmega48P/88P/168P LSB R/W R/W R/W R SPDR Undefined 173 ...
Page 174
... Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. ATmega48P/88P/168P 174 ”Minimizing Power Consumption” on page 43 Figure 20-1 on page 8025M– ...
Page 175
... The XCKn pin is only active when using synchronous mode. 8025M–AVR–6/11 (1) UBRRn [H:L] BAUD RATE GENERATOR UDRn(Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDRn (Receive) UCSRnA 1. Refer to Figure 1-1 on page 2 and ATmega48P/88P/168P Clock Generator OSC SYNC LOGIC PIN CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN CONTROL ...
Page 176
... Receiver’s clock and data recovery units. However, the recovery units use a state machine that uses states depending on mode set by the state of the UMSELn, U2Xn and DDR_XCKn bits. ATmega48P/88P/168P 176 shows a block diagram of the clock generation logic. ...
Page 177
... BAUD BAUD BAUD 1. The baud rate is defined to be the transfer rate in bit per second (bps) Baud rate (in bits per second, bps) System Oscillator clock frequency Contents of the UBRRnH and UBRRnL Registers, (0-4095) 198). ATmega48P/88P/168P Equation for Calculating (1) Rate UBRRn Value UBRRn = f ...
Page 178
... The USART accepts all 30 combinations of the following as valid frame formats: • 1 start bit • data bits • no, even or odd parity bit • stop bits ATmega48P/88P/168P 178 Figure 20-2 for details. depends on the stability of the system clock source therefore recommended to osc ...
Page 179
... even n 1 – ⊕ odd – Parity bit using even parity even odd Parity bit using odd parity Data bit n of the character n ATmega48P/88P/168P FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] … ⊕ ⊕ ⊕ ⊕ ⊕ ...
Page 180
... The following simple USART initialization code examples show one assembly and one C func- tion that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. ATmega48P/88P/168P 180 8025M–AVR–6/11 ...
Page 181
... UCSRnC,r16 ret (1) USART_Init(MYUBRR) /*Set baud rate */ UBRR0H = (unsigned char)(ubrr>>8); UBRR0L = (unsigned char)ubrr; Enable receiver and transmitter */ UCSR0B = (1<<RXEN0)|(1<<TXEN0); /* Set frame format: 8data, 2stop bit */ UCSR0C = (1<<USBS0)|(3<<UCSZ00); 1. See ”About Code Examples” on page 8. ATmega48P/88P/168P 181 ...
Page 182
... Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples ATmega48P/88P/168P 182 (1) UDRn,r16 (1) ...
Page 183
... Put data into buffer, sends the data */ UDRn = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRnB is static. For example, only the TXB8 bit of the UCSRnB Register is used after initialization. 2. See ”About Code Examples” on page 8. ATmega48P/88P/168P 183 ...
Page 184
... Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDRn I/O location. The following code example shows a simple USART receive function based on polling of the Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant ATmega48P/88P/168P 184 8025M–AVR–6/11 ...
Page 185
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega48P/88P/168P 185 ...
Page 186
... Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. ATmega48P/88P/168P 186 (1) r18, UCSRnA r17, UCSRnB ...
Page 187
... The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. 8025M–AVR–6/11 ”Parity Bit Calculation” on page 179 ATmega48P/88P/168P and ”Parity Checker” on page 187. 187 ...
Page 188
... Note the larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (i.e., no communication activity). ATmega48P/88P/168P 188 (1) r16, UDRn (1) 1 ...
Page 189
... RxD Sample (U2X = Sample (U2X = shows the sampling of the stop bit and the earliest possible beginning ATmega48P/88P/168P START Figure 20-6 shows the sampling of the data bits and ...
Page 190
... The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate slow Table 20-2 on page 191 that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. ATmega48P/88P/168P 190 RxD Figure 20-7 ...
Page 191
... Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = (%) R (%) slow fast 5 94.12 105.66 6 94.92 104.92 7 95.52 104,35 8 96.00 103.90 9 96.39 103.53 10 96.70 103.23 ATmega48P/88P/168P Recommended Max Max Total Error (%) Receiver Error (%) +6.67/-6.8 ± 3.0 +5.79/-5.88 ± 2.5 +5.11/-5.19 ± 2.0 +4.58/-4.54 ± 2.0 +4.14/-4.19 ± 1.5 +3.78/-3.83 ± 1.5 Recommended Max Max Total Error (%) Receiver Error (%) +5.66/-5.88 ± 2.5 +4.92/-5.08 ± 2.0 +4.35/-4.48 ± 1.5 +3.90/-4.00 ± 1.5 +3.53/-3.61 ± ...
Page 192
... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. ATmega48P/88P/168P 192 8025M–AVR–6/11 ...
Page 193
... The UDREn Flag can generate a 8025M–AVR–6/ RXB[7:0] TXB[7:0] R/W R/W R/W R RXCn TXCn UDREn FEn R R ATmega48P/88P/168P R/W R/W R/W R DORn UPEn U2Xn MPCMn R R R/W R UDRn (Read) UDRn (Write) UCSRnA ...
Page 194
... Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. ATmega48P/88P/168P 194 ”Multi-processor Communication Mode” on page ...
Page 195
... UMSELn1 UMSELn0 UPMn1 R/W R/W R UMSELn Bits Settings UMSELn0 See ”USART in SPI Mode” on page 202 operation ATmega48P/88P/168P UPMn0 USBSn UCSZn1 UCSZn0 R/W R/W R/W R Table 20-4. Mode Asynchronous USART Synchronous USART (Reserved) (1) Master SPI (MSPIM) for full description of the Master SPI Mode (MSPIM) ...
Page 196
... Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). ATmega48P/88P/168P 196 UPMn Bits Settings UPMn0 ...
Page 197
... R/W R/W R/W R 190). The error values are calculated using the following equation: BaudRate ⎛ Closest Match Error[%] = ------------------------------------------------- - 1 ⎝ BaudRate ATmega48P/88P/168P Received Data Sampled (Input on RxDn Pin) Falling XCKn Edge Rising XCKn Edge UBRRn[11: R/W R/W R/W R/W R/W R/W R/W R ...
Page 198
... Max. 62.5 kbps 125 kbps Note: 1. UBRRn = 0, Error = 0.0% ATmega48P/88P/168P 198 f = 1.8432 MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.2% 47 0.0% 95 0.2% 23 0.0% 47 0.2% 11 0.0% 23 -3.5% 7 0.0% 15 -7.0% 5 0.0% 11 8.5% 3 0. ...
Page 199
... Mbps ATmega48P/88P/168P f = 7.3728 MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.2% 191 0.0% 383 0.2% 95 0.0% 191 0.2% 47 0.0% 95 -0.8% 31 0.0% 63 0.2% 23 0.0% 47 2.1% 15 0.0% 31 0.2% 11 0.0% 23 -3.5% 7 0.0% 15 -7.0% 5 0.0% 11 8.5% 3 0. ...
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... Max. 0.5 Mbps 1 Mbps 1. UBRRn = 0, Error = 0.0% ATmega48P/88P/168P 200 11.0592 f = MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn -0.1% 287 0.0% 575 0.2% 143 0.0% 287 0.2% 71 0.0% 143 0.6% 47 0.0% 95 0.2% 35 0.0% 71 -0.8% 23 0.0% 47 0.2% 17 0.0% 35 2.1% 11 0.0% 23 ...