ATmega64M1 Automotive Atmel Corporation, ATmega64M1 Automotive Datasheet - Page 17

• Manufacturer Part Number: ATmega64M1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega64M1 Automotive

• Flash (kbytes): 64 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

18
Mnemonics
MOVW
SWAP
PUSH
BSET
BCLR
BRID
BRIE
ROR
MOV
SPM
ROL
ASR
SEC
CLC
SEN
CLN
SES
SEV
SEH
CLH
LDD
LDD
STD
STD
LPM
LPM
LPM
OUT
LSL
LSR
BST
BLD
SEZ
CLZ
CLS
CLV
SET
CLT
LDS
STS
SBI
CBI
SEI
CLI
LDI
LD
LD
LD
LD
LD
LD
LD
LD
LD
ST
ST
ST
ST
ST
ST
ST
ST
ST
IN
ATmega16/32/64/M1/C1
Operands
Rd, Z+q
Rd,Y+q
Rd, X+
Rd, - X
Rd, Y+
Rd, - Y
Rd, Z+
Y+q,Rr
Z+q,Rr
Rd, Z+
Rd, Rr
Rd, Rr
Rd, -Z
X+, Rr
- X, Rr
Y+, Rr
- Y, Rr
Z+, Rr
-Z, Rr
Rd, b
Rd, K
Rd, X
Rd, Y
Rd, Z
Rd, Z
Rd, P
Rd, k
X, Rr
Y, Rr
Z, Rr
P, Rr
Rr, b
k, Rr
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
Rr
s
s
k
k
BIT AND BIT-TEST INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
Load Program Memory and Post-Inc
Clear Twos Complement Overflow
Set Twos Complement Overflow.
Load Indirect with Displacement
Load Indirect with Displacement
Store Indirect with Displacement
Store Indirect with Displacement
Clear Half Carry Flag in SREG
Set Half Carry Flag in SREG
Rotate Right Through Carry
Branch if Interrupt Disabled
Bit Store from Register to T
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Branch if Interrupt Enabled
Rotate Left Through Carry
Bit load from T to Register
Move Between Registers
Load Direct from SRAM
Clear Bit in I/O Register
Global Interrupt Disable
Store Program Memory
Push Register on Stack
Global Interrupt Enable
Clear Signed Test Flag
Load Program Memory
Load Program Memory
Set Bit in I/O Register
Store Direct to SRAM
Arithmetic Shift Right
Set Signed Test Flag
Copy Register Word
Clear Negative Flag
Logical Shift Right
Set Negative Flag
Logical Shift Left
Clear T in SREG
Load Immediate
Clear Zero Flag
Set T in SREG
Description
Swap Nibbles
Set Zero Flag
Store Indirect
Store Indirect
Store Indirect
Load Indirect
Load Indirect
Load Indirect
Clear Carry
Flag Clear
Set Carry
Flag Set
Out Port
In Port
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(n) ← Rd(n+1), n=0..6
Rd ← (X), X ← X + 1
Rd ← (Y), Y ← Y + 1
Rd+1:Rd ← Rr+1:Rr
X ← X - 1, Rd ← (X)
Y ← Y - 1, Rd ← (Y)
(X) ← Rr, X ← X + 1
(Y) ← Rr, Y ← Y + 1
Z ← Z - 1, Rd ← (Z)
X ← X - 1, (X) ← Rr
Y ← Y - 1, (Y) ← Rr
(Z) ← Rr, Z ← Z + 1
Rd ← (Z), Z ← Z+1
Z ← Z - 1, (Z) ← Rr
Rd ← (Z), Z ← Z+1
SREG(s) ← 1
SREG(s) ← 0
STACK ← Rr
Rd ← (Y + q)
Rd ← (Z + q)
Operation
I/O(P,b) ← 1
I/O(P,b) ← 0
(Y + q) ← Rr
(Z + q) ← Rr
(Z) ← R1:R0
Rd(b) ← T
T ← Rr(b)
Rd ← (k)
Rd ← (X)
Rd ← (Y)
Rd ← (Z)
R0 ← (Z)
Rd ← (Z)
(X) ← Rr
(Y) ← Rr
(Z) ← Rr
Rd ← Rr
Rd ← K
(k) ← Rr
Rd ← P
P ← Rr
C ← 1
C ← 0
N ← 1
N ← 0
Z ← 1
Z ← 0
S ← 1
S ← 0
V ← 1
V ← 0
T ← 1
T ← 0
H ← 1
H ← 0
I ← 1
I ← 0
SREG(s)
SREG(s)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
C
C
N
N
H
H
T
Z
Z
S
S
V
V
T
T
I
I
7647DS–AVR–08/08
#Clocks
1/2
1/2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
1
1
2
-