ATtiny10 Atmel Corporation, ATtiny10 Datasheet
ATtiny10
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Features • High Performance, Low Power AVR • Advanced RISC Architecture – 54 Powerful Instructions – Most Single Clock Cycle Execution – General Purpose Working Registers – Fully Static Operation – MIPS Throughput at ...
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Pin Configurations Figure 1-1. (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 1.1 Pin Description 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB3..PB0) This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The ...
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Overview ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize ...
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... Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer. The ATtiny4/5/9/10 AVR are supported by a suite of program and system development tools, including macro assemblers and evaluation kits. 2.1 Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10 A comparison of the devices is shown in Table 2-1. ATtiny4/5/9/10 4 ...
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General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use ...
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CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle ...
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Six of the 16 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look ...
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General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
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Figure 4-3. X-register Y-register Z-register In different addressing modes these address registers function as automatic increment and automatic decrement (see document “AVR Instruction Set” and section mary” on page 152 4.5 Stack Pointer The Stack is mainly used for storing ...
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Figure 4-4. 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 4-4 vard architecture and the fast access Register File concept. This is the basic pipelining concept ...
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The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that ...
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Register Description 4.8.1 CCP – Configuration Change Protection Register Bit 0x3C Read/Write Initial Value • Bits 7:0 – CCP[7:0] – Configuration Change Protection In order to change the contents of a protected I/O register the CCP register must first ...
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Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti- nation for the operated bit. A bit from a register in the Register File ...
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Memories This section describes the different memories in the ATtiny4/5/9/10. Devices have two main memory areas, the program memory space and the data memory space. 5.1 In-System Re-programmable Flash Program Memory The ATtiny4/5/9/10 contain 512/1024 bytes of on-chip, in-system ...
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Figure 5-1. 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 5-2. 8127E–AVR–11/11 Data Memory Map (Byte Addressing) I/O SPACE SRAM ...
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I/O Memory The I/O space definition of the ATtiny4/5/9/10 is shown in All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD and ST instructions, enabling data transfer between ...
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Clock System Figure 6-1 clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes and power reduction reg- ister ...
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ADC Clock – clk ADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. The ...
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Internal 128 kHz Oscillator The internal 128 kHz oscillator is a low power oscillator providing a clock of 128 kHz. The fre- quency depends on supply voltage, temperature and batch variations. This clock may be select as the main ...
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Starting 6.4.1 Starting from Reset The internal reset is immediately asserted when a reset source goes active. The internal reset is kept asserted until the reset source is released and the start-up sequence is completed. The start-up sequence includes ...
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Register Description 6.5.1 CLKMSR – Clock Main Settings Register Bit 0x37 Read/Write Initial Value • Bit 7:2 – Res: Reserved Bits These bits are reserved and always read zero. • Bit 1:0 – CLKMS[1:0]: Clock Main Select Bits These ...
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CLKPSR – Clock Prescale Register Bit 0x36 Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits ...
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Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, ...
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ACD bit in Control and Status Register” on page ADC is enabled (ATtiny5/10, only), a conversion starts automatically when this mode is entered. 7.1.2 ADC Noise Reduction Mode When bits SM2:0 ...
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Analog Comparator When entering Idle mode, the analog comparator should be disabled if not used. In the power- down mode, the analog comparator is automatically disabled. See page 82 7.3.2 Analog to Digital Converter If enabled, the ADC will ...
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Bits 3:1 – SM2..SM0: Sleep Mode Select Bits 2..0 These bits select between available sleep modes, as shown in Table 7-2. SM2 Note: • Bit 0 – SE: Sleep Enable The ...
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System Control and Reset 8.1 Resetting the AVR During reset, all I/O registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP ...
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Power-on Reset A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in section whenever V Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ...
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The VLM can also be used to improve reset characteristics at falling supply. Without VLM, the Power-On Reset (POR) does not activate before supply voltage has dropped to a level where the MCU is not necessarily functional any more. With ...
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Watchdog Timer and reset time-out. Figure 8-5. CC 8.3 Watchdog Timer The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128 kHz. See 6. By controlling the Watchdog Timer prescaler, ...
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To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in See “Procedure for Changing the Watchdog Timer Configuration” on page 31 Table 8-1. WDTON ...
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Code Examples The following code example shows how to turn off the WDT. The example assumes that inter- rupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code ...
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Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a Sys- tem Reset will be applied. Table 8-2. WDTON Note: • Bit 4 – Res: Reserved Bit This bit is ...
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Bits 5, 2:0 – WDP3..0: Watchdog Timer Prescaler and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown ...
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Bits 2:0 – VLM2:0: Trigger Level of Voltage Level Monitor These bits set the trigger level for the voltage level monitor, as described in Table 8-4. VLM2:0 000 001 010 011 100 101 110 111 For VLM voltage levels, ...
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Interrupts This section describes the specifics of the interrupt handling in ATtiny4/5/9/10. For a general explanation of the AVR interrupt handling, see 9.1 Interrupt Vectors Interrupt vectors of ATtiny4/5/9/10 are described in Table 9-1. Vector No ...
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External Interrupts External Interrupts are triggered by the INT0 pin or any of the PCINT3..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT3..0 pins ...
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Figure 9-1. PCINT(0) PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF 9.3 Register Description 9.3.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 0x15 Read/Write Initial Value • ...
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Table 9-2. ISC01 9.3.2 EIMSK – External Interrupt Mask Register Bit 0x13 Read/Write Initial Value • Bits ...
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PCICR – Pin Change Interrupt Control Register Bit 0x12 Read/Write Initial Value • Bits 7:1 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 0 – PCIE0: Pin Change Interrupt Enable 0 When ...
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I/O Ports 10.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O Pxn Note: 10.2.1 Configuring the Pin Each port pin ...
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The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If ...
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Figure 10-3. Switching Between Input and Output in Break-Before-Make-Mode SYSTEM CLK INSTRUCTIONS 10.2.4 Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in ...
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When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 10-5. Synchronization ...
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Program Example The following code example shows how to set port B pin 0 high, pin 1 low, and define the port pins from input with a pull-up assigned to port pin 2. The resulting ...
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Figure 10-6. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: PTOExn: Note: The illustration in the figure above serves as a generic description applicable to all port pins in the AVR microcontroller family. Some overriding ...
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Table 10-2 on page 48 indexes from signals are generated internally in the modules having the alternate function. Table 10-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate ...
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Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-3. • Port B, Bit 0 – ADC0/AIN0/OC0A/PCINT0/TPIDATA • ADC0: Analog to Digital Converter, Channel 0 • AIN0: Analog Comparator Positive Input. Configure ...
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OC0B: Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter0 Compare Match B. The PB1 pin has to be configured as an output (DDB1 set (one)) to serve this function. The OC0B ...
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Table 10-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Notes: 10.4 Register Description 10.4.1 PORTCR – Port Control Register Bit 0x03 Read/Write Initial Value • Bits 7:2, 0 – Reserved These bits are reserved ...
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PORTB – Port B Data Register Bit 0x02 Read/Write Initial Value 10.4.4 DDRB – Port B Data Direction Register Bit 0x01 Read/Write Initial Value 10.4.5 PINB – Port B Input Pins Bit 0x00 Read/Write Initial Value ATtiny4/5/9/ ...
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Timer/Counter0 11.1 Features • True 16-bit Design, Including 16-bit PWM • Two Independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on Compare Match ...
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A simplified block diagram of the 16-bit Timer/Counter is shown in actual placement of I/O pins, refer to Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the ...
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Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter control ...
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N+1 sys- tem clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024 possible to use the ...
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Figure 11-4. Counter Unit Block Diagram TCNTnH (8-bit) Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT0H) con- taining the upper eight bits of the ...
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Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul- tiple events, can be applied via the ...
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TOP value can be written to the ICR0 Register. When writing the ICR0 Register the high byte must be written to the ICR0H I/O location before the low byte is written ...
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I/O bit location). For measuring frequency only, the clearing of the ICF0 flag is not required (if an interrupt handler is used). 11.6 Output Compare Units The 16-bit comparator continuously compares ...
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The double buffering synchronizes the update of the OCR0x Com- pare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out- put ...
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Compare Match Output Unit The Compare Output Mode (COM0x1:0) bits have two functions. The Waveform Generator uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next compare match. Secondly the COM0x1:0 bits control the OC0x ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register ...
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The timing diagram for the CTC mode is shown in (TCNT0) increases until a compare match occurs with either OCR0A or ICR0, and then counter (TCNT0) is cleared. Figure 11-8. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt ...
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PWM mode can be twice as high as the phase cor- rect and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited ...
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The procedure for updating ICR0 differs from updating OCR0A when used for defining the TOP value. The ICR0 Register is not double buffered. This means that if ICR0 is changed to a low value when the counter is running with ...
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However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by ...
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Compare Registers, a compare match will never occur between the TCNT0 and the OCR0x. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR0x Registers are written. As the third period ...
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OCR0A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either ...
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Using the ICR0 Register for defining TOP works well when using fixed TOP values. By using ICR0, the OCR0A Register is free to be used for generating a PWM output on OC0A. However, if the base PWM frequency is actively ...
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Figure 11-13 on page 71 Figure 11-13. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRnx OCFnx Figure 11-14 on page 71 using phase and frequency correct PWM mode the OCR0x ...
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Figure 11-15. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOVn and ICF n as TOP) OCRnx (Update at TOP) 11.10 Accessing 16-bit Registers The TCNT0, OCR0A/B, and ICR0 are ...
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Assembly Code Example Note: The code example returns the TCNT0 value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions accessing the 16-bit register, ...
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Assembly Code Example TIM16_WriteTCNT0: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT0 to r17:r16 out TCNT0H,r17 out TCNT0L,r16 ; Restore global interrupt flag out SREG,r18 ret Note: The code example requires that the r17:r16 ...
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When OC0A or OC0B is connected to the pin, the function of COM0x1:0 bits depends on the WGM03:0 bits Normal or CTC (non-PWM) Mode. Table 11-2. COM0A1/ COM0B1 Table 11-3 Fast PWM Modes. Table 11-3. COM0A1/ COM0B1 1 ...
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Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with WGM03:2 bits of TCCR0B, these bits control the counting sequence of the coun- ter, the source for maximum (TOP) counter value, and what type of waveform to generate. See Table ...
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When a capture is triggered according to the ICES0 setting, the counter value is copied into the Input Capture Register (ICR0). The event will also set the Input Capture Flag (ICF0), and this can be used to cause an Input ...
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The OC0A/OC0B output is changed according to its COM0x1:0 bits setting. Note that the FOC0A/FOC0B bits are implemented as strobes. Therefore it is the value present in the COM0x1:0 bits that determine the effect of the forced compare. A FOC0A/FOC0B ...
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This temporary register is shared by all the other 16- bit registers. See 11.11.7 ICR0H and ICR0L – Input Capture Register 0 Bit 0x23 0x22 Read/Write Initial Value The Input Capture is updated with ...
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TIFR0 – Timer/Counter Interrupt Flag Register 0 Bit 0x2A Read/Write Initial Value • Bits 7:6, 4:3 – Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to zero ...
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This ensures that the Timer/Counter is halted and can be configured without the risk of advanc- ing during configuration. When the TSM bit is written to zero, the PSR bit is cleared by hardware, and the Timer/Counter start counting. • ...
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Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator ...
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Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The analog comparator interrupt routine is executed if the ACIE bit ...
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Analog to Digital Converter 13.1 Features • 8-bit Resolution • 0.5 LSB Integral Non-linearity • ± 1 LSB Absolute Accuracy • 65µs Conversion Time • 15 kSPS at Full Resolution • Four Multiplexed Single Ended Input Channels • Input ...
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Figure 13-1. Analog to Digital Converter Block Schematic V CC ADC3 ADC2 ADC1 ADC0 13.4 Starting a Conversion Make sure the ADC is powered by clearing the ADC Power Reduction bit, PRADC, in the Power Reduction Register, PRR (see A ...
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Figure 13-2. ADC Auto Trigger Logic Using the ADC interrupt flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, con- stantly ...
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ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC ...
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Figure 13-6. ADC Timing Diagram, Auto Triggered Conversion Cycle Number ADC Clock Trigger Source ADATE ADIF ADCL In Free Running mode (see conversion completes, while ADSC remains high. Figure 13-7. ADC Timing Diagram, Free Running Conversion For a summary of ...
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Changing Channel The MUXn bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channel selection only takes place at a safe point during the conversion. ...
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Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. • Enter ADC Noise Reduction mode (or Idle mode). The ADC will ...
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Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. When conversion accuracy is critical, the noise level can be reduced by applying the following techniques: • Keep analog ...
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Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0xFE to 0xFF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 13-10. Gain Error ...
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Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 13-12. Differential Non-linearity (DNL) • Quantization Error: Due to the ...
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Register Description – 13.12.1 ADMUX ADC Multiplexer Selection Register Bit 0x1B Read/Write Initial Value • Bits 7:2 – Res: Reserved Bits These bits are reserved and will always read zero. • Bits 1:0 – MUX1:0: Analog Channel Selection Bits ...
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Bit 4 – ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is requested if the ADIE bit is set. ADIF is cleared by ...
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If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set Table 13-4. ADTS2 – 13.12.4 ADCL ADC ...
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Programming interface 14.1 Features • Physical Layer: – Synchronous Data Transfer – Bi-directional, Half-duplex Receiver And Transmitter – Fixed Frame Format With One Start Bit, 8 Data Bits, One Parity Bit And 2 Stop Bits – Parity Error Detection, ...
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The TPI is accessed via three pins, as follows: RESET: TPICLK: TPIDATA: In addition, the V device. See Figure 14-2. Using an External Programmer for In-System Programming via TPI NVM can be programmed at 5V, only. In some designs it ...
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Disabling Provided that the NVM enable bit has been cleared, the TPI is automatically disabled if the RESET pin is released to inactive high state or, alternatively RESET pin. If the NVM enable bit is not cleared ...
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Operation The TPI physical layer operates synchronously on the TPICLK provided by the external pro- grammer. The dependency between the clock edges and data sampling or data change is shown in Figure 14-6. Data changing and Data sampling. The ...
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Collision Detection Exception The TPI physical layer uses one bi-directional data line for both data reception and transmission. A possible drive contention may occur, if the external programmer and the TPI physical layer drive the TPIDATA line simultaneously. In ...
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The TPI access layer controls the character transfer direction on the TPI physical layer. It also handles the recovery from the error state after exception. The Control and Status Space (CSS) of the Tiny Programming Interface is allocated for control ...
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Instruction Set The TPI has a compact instruction set that is used to access the TPI Control and Status Space (CSS) and the data space. The instructions allow the external programmer to access the TPI, the NVM Controller and ...
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The Pointer Register can be either left unchanged by the operation can be post-incremented, as shown in Table 14-3. Operation DS[PR] DS[PR] 14.5.3 SSTPR - Serial STore to ...
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SLDCS - Serial LoaD data from Control and Status space using direct addressing The SLDCS instruction loads data byte from the TPI Control and Status Space to the TPI physi- cal layer shift register for serial read-out. The SLDCS ...
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Control and Status Space Register Descriptions The control and status registers of the Tiny Programming Interface are mapped in the Control and Status Space (CSS) of the interface. These registers are not part of the I/O register map and ...
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Bits 2:0 – GT[2:0]: Guard Time These bits specify the number of additional IDLE bits that are inserted to the idle time when changing from reception mode to transmission mode. Additional delays are not inserted when changing from transmission ...
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Memory Programming 15.1 Features • Two Embedded Non-Volatile Memories: – Non-Volatile Memory Lock bits (NVM Lock bits) – Flash Memory • Four Separate Sections Inside Flash Memory: – Code Section (Program Memory) – Signature Section – Configuration Section – ...
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Non-Volatile Memories The ATtiny4/5/9/10 have the following, embedded NVM: • Non-Volatile Memory Lock Bits • Flash memory with four separate sections 15.3.1 Non-Volatile Memory Lock Bits The ATtiny4/5/9/10 provide two Lock Bits, as shown in Table 15-1. Lock Bit ...
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Flash Memory The embedded Flash memory of ATtiny4/5/9/10 has four separate sections, as shown in 15-3 and Table 15-3. Section Code (program memory) Configuration Signature Calibration Notes: Table 15-4. Section Code (program memory) Configuration Signature Calibration Notes: 15.3.3 Configuration ...
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... Table 15-8. Part ATtiny4 ATtiny5 ATtiny9 ATtiny10 15.3.5 Calibration Section ATtiny4/5/9/10 have one calibration byte. The calibration byte contains the calibration data for the internal oscillator and resides in the calibration section, as shown in reset, the calibration byte is automatically written into the OSCCAL register to ensure correct fre- quency of the calibrated internal oscillator ...
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Latching of Calibration Value To ensure correct frequency of the calibrated internal oscillator the calibration value is automati- cally written into the OSCCAL register during reset. 15.4 Accessing the NVM NVM lock bits, and all Flash memory sections are ...
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Figure 15-1. Addressing the Flash Memory 16 ADDRESS POINTER SECTIONEND 15.4.2 Reading the Flash The Flash can be read from the data memory mapped locations one byte at a time. For read operations, the least significant bit (bit 0) is ...
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Before starting the Chip erase, the NVMCMD register must be loaded with the CHIP_ERASE command. To start the erase operation a dummy byte must be written into the high byte of a word location that resides inside the Flash code ...
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Reading NVM Lock Bits The Non-Volatile Memory Lock Byte can be read from the mapped location in data memory. 15.4.5 Writing NVM Lock Bits The algorithm for writing the Lock bits is as follows. 1. Write the WORD_WRITE command ...
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Register Description 15.7.1 NVMCSR - Non-Volatile Memory Control and Status Register Bit 0x32 Read/Write Initial Value • Bit 7 - NVMBSY: Non-Volatile Memory Busy This bit indicates the NVM memory (Flash memory and Lock Bits) is busy, being programmed. ...
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Electrical Characteristics 16.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0. Voltage on RESET with respect to Ground......-0.5V to +13.0V ...
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Table 16-1. DC Characteristics. T Symbol Parameter (6) Power Supply Current I CC (7) Power-down mode Notes: 1. “Min” means the lowest value where the pin is guaranteed to be read as high. 2. “Max” means the highest value where ...
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Clock Characteristics 16.4.1 Accuracy of Calibrated Internal Oscillator It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics ...
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System and Reset Characteristics Table 16-4. Symbol V RST t RST t TOUT Note: 16.5.1 Power-On Reset Table 16-5. Symbol V POR V POA SR ON Note: 16.5.2 V Level Monitor CC Table 16-6. Parameter Trigger level VLM1L Trigger ...
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Analog Comparator Characteristics Table 16-7. Analog Comparator Characteristics, T Symbol Parameter V Input Offset Voltage AIO I Input Leakage Current LAC Analog Propagation Delay (from saturation to slight overdrive) t APD Analog Propagation Delay (large step change) t Digital ...
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Serial Programming Characteristics Figure 16-3. Serial Programming Timing TPIDATA t IVCH TPICLK Table 16-9. Symbol 1/t CLCL t CLCL t CLCH t CHCH t IVCH t CHIX t CLOV ATtiny4/5/9/10 122 Receive Mode t CHIX t t CLCH CHCL ...
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Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indica- tions of how the part will ...
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Active Supply Current Figure 17-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) Figure 17-2. Active Supply Current vs. frequency ( MHz) 4.5 3.5 2.5 1.5 0.5 ATtiny4/5/9/10 124 ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY ...
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Figure 17-3. Active Supply Current vs. V Figure 17-4. Active Supply Current vs. V 8127E–AVR–11/11 ACTIVE SUPPLY CURRENT vs. V 3.5 3 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 ACTIVE SUPPLY CURRENT vs. V INTERNAL OSCILLATOR, 1 ...
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Figure 17-5. Active Supply Current vs. V Figure 17-6. Active Supply Current vs. V 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 ATtiny4/5/9/10 126 CC ACTIVE SUPPLY CURRENT vs. V INTERNAL OSCILLATOR, 128 KHz 0.12 0.1 0.08 0.06 0.04 0.02 ...
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Idle Supply Current Figure 17-7. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) 0,1 0,09 0,08 0,07 0,06 0,05 0,04 0,03 0,02 0,01 Figure 17-8. Idle Supply Current vs. Frequency ( MHz) 0,8 0,6 0,4 ...
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Figure 17-9. Idle Supply Current vs. V 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 1,5 Figure 17-10. Idle Supply Current vs. V 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 1,5 ATtiny4/5/9/10 128 (Internal Oscillator, 8 MHz) CC IDLE ...
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Power-down Supply Current Figure 17-11. Power-down Supply Current vs. V Figure 17-12. Power-down Supply Current vs 8127E–AVR–11/11 POWER-DOWN SUPPLY CURRENT vs. V 0.5 0.45 0.4 0.35 0.3 0.25 ...
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Pin Pull-up Figure 17-13. I/O pin Pull-up Resistor Current vs. Input Voltage ( Figure 17-14. I/O Pin Pull-up Resistor Current vs. input Voltage ( ...
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Figure 17-15. I/O pin Pull-up Resistor Current vs. Input Voltage (V 160 140 120 100 Figure 17-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage ( ...
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Figure 17-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage ( Figure 17-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 120 100 ATtiny4/5/9/10 132 ...
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Pin Driver Strength Figure 17-19. I/O Pin Output Voltage vs. Sink Current (V Figure 17-20. I/O Pin Output Voltage vs. Sink Current (V 8127E–AVR–11/11 I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ...
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Figure 17-21. I/O pin Output Voltage vs. Sink Current (V Figure 17-22. I/O Pin Output Voltage vs. Source Current (V ATtiny4/5/9/10 134 I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT 1 0.8 0.6 0.4 0 ...
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Figure 17-23. I/O Pin Output Voltage vs. Source Current (V Figure 17-24. I/O Pin output Voltage vs. Source Current (V 5.2 4.8 4.6 4.4 4.2 8127E–AVR–11/11 I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 3.1 2.9 2.7 2.5 2.3 2.1 1.9 ...
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Figure 17-25. Reset Pin as I/O, Output Voltage vs. Sink Current Figure 17-26. Reset Pin as I/O, Output Voltage vs. Source Current ATtiny4/5/9/10 136 OUTPUT VOLTAGE vs. SINK CURRENT 1 1.8 V 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 ...
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Pin Threshold and Hysteresis Figure 17-27. I/O Pin Input Threshold Voltage vs. V 3,5 3 2,5 2 1,5 1 0,5 0 Figure 17-28. I/O Pin Input threshold Voltage vs 2,5 2 1,5 1 0,5 0 8127E–AVR–11/11 I/O ...
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Figure 17-29. I/O Pin Input Hysteresis vs 0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 1,5 Figure 17-30. Reset Pin as I/O, Input Threshold Voltage vs 2,5 2 1,5 1 0,5 0 1,5 ATtiny4/5/9/10 ...
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Figure 17-31. Reset Pin as I/O, Input Threshold Voltage vs. V 2,5 2 1,5 1 0,5 0 Figure 17-32. Reset Input Hysteresis vs 0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 8127E–AVR–11/11 RESET PIN AS I/O ...
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Figure 17-33. Reset Input Threshold Voltage vs. V 2,5 2 1,5 1 0,5 0 1,5 Figure 17-34. Reset Input Threshold Voltage vs. V 2,5 2 1,5 1 0,5 0 1,5 ATtiny4/5/9/10 140 RESET INPUT THRESHOLD VOLTAGE vs. V -40 °C ...
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Figure 17-35. Reset Pin, Input Hysteresis vs 0,8 0,6 0,4 0,2 0 17.8 Analog Comparator Offset Figure 17-36. Analog Comparator Offset 8127E–AVR–11/11 RESET PIN INPUT HYSTERESIS vs. V -40 °C 25 °C 85 °C 1,5 2 2,5 3 ...
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Internal Oscillator Speed Figure 17-37. Watchdog Oscillator Frequency vs. V Figure 17-38. Watchdog Oscillator Frequency vs. Temperature ATtiny4/5/9/10 142 WATCHDOG OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 110 109 108 107 106 105 104 103 102 101 100 99 1.5 2 ...
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Figure 17-39. Calibrated Oscillator Frequency vs. V Figure 17-40. Calibrated Oscillator Frequency vs. Temperature 8127E–AVR–11/11 CALIBRATED 8.0MHz OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 8.4 8.2 8 7.8 7.6 7.4 1.5 2 2.5 3 CALIBRATED 8.0MHz OSCILLATOR FREQUENCY vs. TEMPERATURE 8.3 8.2 ...
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Figure 17-41. Calibrated Oscillator Frequency vs, OSCCAL Value 17.10 VLM Thresholds Figure 17-42. VLM1L Threshold of V 1.42 1.41 1.4 1.39 1.38 1.37 1.36 1.35 1.34 ATtiny4/5/9/10 144 CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE ...
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Figure 17-43. VLM1H Threshold of V 1.65 1.55 1.45 Figure 17-44. VLM2 Threshold of V 8127E–AVR–11/11 Level Monitor CC VLM THRESHOLD vs. TEMPERATURE 1.7 1.6 1.5 1.4 -40 -20 0 Temperature (C) Level Monitor CC VLM THRESHOLD vs. TEMPERATURE 2.48 ...
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Figure 17-45. VLM3 Threshold of V 17.11 Current Consumption of Peripheral Units Figure 17-46. ADC Current vs. V ATtiny4/5/9/10 146 Level Monitorr2 CC VLM THRESHOLD vs. TEMPERATURE 3.9 3.8 3.7 3.6 3.5 3.4 -40 - Temperature (C) (ATtiny5/10, ...
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Figure 17-47. Analog Comparator Current vs. V 140 120 100 Figure 17-48. V 8127E–AVR–11/11 ANALOG COMPARATOR CURRENT vs 1,5 2 2,5 3 Level Monitor Current vs VLM SUPPLY CURRENT vs. V 0.35 ...
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Figure 17-49. Temperature Dependence of VLM Current vs. V 350 300 250 200 150 100 50 Figure 17-50. Watchdog Timer Current vs ATtiny4/5/9/10 148 VLM SUPPLY CURRENT vs. V ...
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Current Consumption in Reset and Reset Pulsewidth Figure 17-51. Reset Supply Current vs. V 0,5 0,4 0,3 0,2 0,1 0 Note: Figure 17-52. Minimum Reset Pulse Width vs. V 2500 2000 1500 1000 500 0 8127E–AVR–11/11 Reset Pull-up) RESET ...
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Register Summary Address Name Bit 7 0x3F SREG I 0x3E SPH 0x3D SPL 0x3C CCP 0x3B RSTFLR – 0x3A SMCR – 0x39 OSCCAL 0x38 Reserved – 0x37 CLKMSR – 0x36 CLKPSR – 0x35 PRR – 0x34 VLMCSR VLMF 0x33 ...
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Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add without Carry ADC Rd, Rr Add with Carry SUB Rd, Rr Subtract without Carry SUBI Rd, K Subtract Immediate SBC Rd, Rr Subtract with Carry SBCI ...
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Mnemonics Operands BCLR s Flag Clear SBI A, b Set Bit in I/O Register CBI A, b Clear Bit in I/O Register BST Rr, b Bit Store from Register to T BLD Rd, b Bit load from T to Register ...
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Ordering Information 20.1 ATtiny4 Supply Voltage Speed 12 MHz 1.8 – 5.5V 10 MHz Notes: 1. For speed vs. supply voltage, see section 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive ...
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ATtiny5 Supply Voltage Speed 12 MHz 1.8 – 5.5V 10 MHz Notes: 1. For speed vs. supply voltage, see section 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of ...
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ATtiny9 Supply Voltage Speed 12 MHz 1.8 – 5.5V 10 MHz Notes: 1. For speed vs. supply voltage, see section 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of ...
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... Plastic Ultra Thin Dual Flat No Lead (UDFN) 8127E–AVR–11/11 (1) Temperature Industrial (4) (-40°C to 85°C) Extended (7) (-40°C to 125°C) 16.3 “Speed” on page 118. Package Type ATtiny4/5/9/10 (2) (3) Package Ordering Code (5) 6ST1 ATtiny10-TSHR (6) 8MA4 ATtiny10-MAHR (5) 6ST1 ATtiny10-TS8R 157 ...
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Packaging Information 21.1 6ST1 Pin # Top View 0. View B Notes: 1. This package is compliant with JEDEC specification MO-178 Variation AB 2. Dimension D does ...
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E Pin TOP VIEW C0.2 4 BOTTOM VIEW Note: 1. ALL DIMENSIONS ARE IN mm. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL ...
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Errata The revision letters in this section refer to the revision of the corresponding ATtiny4/5/9/10 device. 22.1 ATtiny4 22.1.1 Rev. E • Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower ...
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Rev. D • ESD HBM (ESD STM 5.1) level ±1000V • Programming Lock Bits 1. ESD HBM (ESD STM 5.1) level ±1000V The device meets ESD HBM (ESD STM 5.1) level ±1000V. Problem Fix / Workaround Always use proper ...
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... Rev. A – C Not sampled. 22.4 ATtiny10 22.4.1 Rev. E • Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. ...
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... Also, updated some other plots in Typical Characteristics. 154 page 157 Section 22. “Errata” on page 160 “Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10” on page 4 “ADC Clock – clkADC” on page 18 “Starting from Idle / ADC Noise Reduction / Standby Mode” on page 20 “ADC Noise Reduction Mode” on page 24 “ ...
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Added figure: – 6. Updated figure: – 7. Added table: – 8. Updated tables: – – – – 23.5 Rev. 8127A – 04/09 1. Initial revision ATtiny4/5/9/10 164 “Overview” on page 84 ...
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... General Information ................................................................................. 5 4 CPU Core .................................................................................................. 6 5 Memories ................................................................................................ 14 6 Clock System ......................................................................................... 17 7 Power Management and Sleep Modes ................................................. 23 8127E–AVR–11/11 1.1 Pin Description ..................................................................................................2 2.1 Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10 ...................................4 3.1 Resources .........................................................................................................5 3.2 Code Examples .................................................................................................5 3.3 Data Retention ...................................................................................................5 3.4 Disclaimer ..........................................................................................................5 4.1 Architectural Overview .......................................................................................6 4.2 ALU – Arithmetic Logic Unit ...............................................................................7 4.3 Status Register ..................................................................................................7 4 ...
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System Control and Reset .................................................................... 27 9 Interrupts ................................................................................................ 36 10 I/O Ports .................................................................................................. 41 11 16-bit Timer/Counter0 ............................................................................ 53 12 Analog Comparator ............................................................................... 82 13 Analog to Digital Converter .................................................................. 84 ATtiny4/5/9/10 ii 7.3 Minimizing Power Consumption ......................................................................24 ...
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Programming interface .......................................................................... 97 15 Memory Programming ......................................................................... 108 16 Electrical Characteristics .................................................................... 117 17 Typical Characteristics ........................................................................ 123 8127E–AVR–11/11 13.4 Starting a Conversion ......................................................................................85 13.5 Prescaling and Conversion Timing ..................................................................86 13.6 Changing Channel ...........................................................................................89 13.7 ADC Noise Canceler ...
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... Current Consumption in Reset and Reset Pulsewidth ..................................149 20.1 ATtiny4 ..........................................................................................................154 20.2 ATtiny5 ..........................................................................................................155 20.3 ATtiny9 ..........................................................................................................156 20.4 ATtiny10 ........................................................................................................157 21.1 6ST1 ..............................................................................................................158 21.2 8MA4 .............................................................................................................159 22.1 ATtiny4 ..........................................................................................................160 22.2 ATtiny5 ..........................................................................................................160 22.3 ATtiny9 ..........................................................................................................161 22.4 ATtiny10 ........................................................................................................162 23.1 Rev. 8127D – 02/10 .......................................................................................163 23.2 Rev. 8127C – 10/09 .......................................................................................163 23.3 Rev. 8127B – 08/09 .......................................................................................163 23.4 Rev. 8127A – 04/09 .......................................................................................164 8127E–AVR–11/11 ...
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ATtiny4/5/9/10 v ...
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... Atmel Corporation. All rights reserved. ® Atmel , logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia Limited Atmel Munich GmbH Unit 01-5 & ...