ATtiny13 Atmel Corporation, ATtiny13 Datasheet - Page 93
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATtiny13
Manufacturer Part Number
ATtiny13
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny13
Flash (kbytes)
1 Kbytes
Pin Count
8
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.06
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
2
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATtiny13-10SSU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATtiny13-12SI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATtiny13-16PI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATtiny13-20MI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATtiny13-20PU
Manufacturer:
NXP
Quantity:
2 000
Company:
Part Number:
ATtiny13-20PU
Manufacturer:
Atmel
Quantity:
37 287
Part Number:
ATtiny13-20SSI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATtiny13-20SSU-SL383
Manufacturer:
ATMEL
Quantity:
4 132
Company:
Part Number:
ATtiny13A-MMU
Manufacturer:
DP
Quantity:
34 000
Company:
Part Number:
ATtiny13A-MMUR
Manufacturer:
TI
Quantity:
4 430
14.12.3
14.12.3.1
14.12.3.2
2535J–AVR–08/10
ADCL and ADCH – The ADC Data Register
ADLAR = 0
ADLAR = 1
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-
rupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock
to the ADC.
Table 14-4.
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ADPS2
0
0
0
0
1
1
1
1
ADC Prescaler Selections
ADC7
ADC9
ADC1
15
15
R
R
R
R
–
7
0
0
7
0
0
ADC6
ADC8
ADC0
14
14
ADPS1
R
R
R
R
–
6
0
0
6
0
0
0
0
1
1
0
0
1
1
ADC5
ADC7
13
13
R
R
R
R
–
5
0
0
–
5
0
0
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
ADPS0
0
1
0
1
0
1
0
1
ADC3
ADC5
11
11
R
R
R
R
–
3
0
0
–
3
0
0
ADC2
ADC4
10
10
R
R
R
R
–
2
0
0
–
2
0
0
ADC9
ADC1
ADC3
Division Factor
R
R
R
R
9
1
0
0
9
–
1
0
0
128
16
32
64
2
2
4
8
ADC8
ADC0
ADC2
8
0
R
R
0
0
8
–
0
R
R
0
0
ADCH
ADCH
ADCL
ADCL
93