ATtiny26 Atmel Corporation, ATtiny26 Datasheet - Page 8
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ATtiny26
Manufacturer Part Number
ATtiny26
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny26
Flash (kbytes)
2 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
11
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY26
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATtiny26-16MI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATtiny26-16MU
Manufacturer:
ATMEL
Quantity:
7 119
Part Number:
ATtiny26-16SC
Manufacturer:
MITEL
Quantity:
20 000
Part Number:
ATtiny26-16SI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATtiny26-16SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATtiny26-8PI
Manufacturer:
UTC
Quantity:
15
Company:
Part Number:
ATtiny26-8SI
Manufacturer:
INTEL
Quantity:
8
Company:
Part Number:
ATtiny26-8SU
Manufacturer:
ATMTLL
Quantity:
5 510
Company:
Part Number:
ATtiny26-8SU
Manufacturer:
SIEMENS
Quantity:
5 510
Instruction Set Summary
8
Mnemonic
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
ORI
EOR
COM
NEG
SBR
CBR
INC
DEC
TST
CLR
SER
BRANCH INSTRUCTIONS
RJMP
IJMP
RCALL
ICALL
RET
RETI
CPSE
CP
CPC
CPI
SBRC
SBRS
SBIC
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
DATA TRANSFER INSTRUCTIONS
MOV
LDI
LD
LD
LD
ATtiny26(L)
Operands
Rd, Rr
Rd, Rr
Rdl, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Rd
Rd, K
Rd, K
Rd
Rd
Rd
Rd
Rd
k
k
Rd, Rr
Rd, Rr
Rd, Rr
Rd, K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
Rd, Rr
Rd, K
Rd, X
Rd, X+
Rd, -X
Description
Add Two Registers
Add with Carry Two Registers
Add Immediate to Word
Subtract Two Registers
Subtract Constant from Register
Subtract with Carry Two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Decrement
Test for Zero or Minus
Clear Register
Set Register
Relative Jump
Indirect Jump to (Z)
Relative Subroutine Call
Indirect Call to (Z)
Subroutine Return
Interrupt Return
Compare, Skip if Equal
Compare
Compare with Carry
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less than Zero, Signed
Branch if Half-carry Flag Set
Branch if Half-carry Flag Cleared
Branch if T-flag Set
Branch if T-flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
Move between Registers
Load Immediate
Load Indirect
Load Indirect and Post-inc.
Load Indirect and Pre-dec.
Operation
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Rd ← Rd v Rr
Rd ← Rd v K
Rd ← Rd ⊕ Rr
Rd ← $FF - Rd
Rd ← $00 - Rd
Rd ← Rd v K
Rd ← Rd • ($FF - K)
Rd ← Rd + 1
Rd ← Rd - 1
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← $FF
PC ← PC + k + 1
PC ← Z
PC ← PC + k + 1
PC ← Z
PC ← STACK
PC ← STACK
if (Rd = Rr) PC ← PC + 2 or 3
Rd - Rr
Rd - Rr - C
Rd - K
if (Rr(b) = 0) PC ← PC + 2 or 3
if (Rr(b) = 1) PC ← PC + 2 or 3
if (P(b) = 0) PC ← PC + 2 or 3
if (P(b) = 1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC ← PC + k + 1
if (SREG(s) = 0) then PC ← PC + k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V = 0) then PC ← PC + k + 1
if (N ⊕ V = 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if (I = 1) then PC ← PC + k + 1
if (I = 0) then PC ← PC + k + 1
Rd ← Rr
Rd ← K
Rd ← (X)
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Flags
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
None
None
I
None
Z,N,V,C,H
Z,N,V,C,H
Z,N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1477KS–AVR–08/10
# Clocks
1/2/3
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
4
4
1
1
1
1
1
2
2
2