ATtiny45 Automotive Atmel Corporation, ATtiny45 Automotive Datasheet - Page 162
ATtiny45 Automotive
Manufacturer Part Number
ATtiny45 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY25_AUTOMOTIVE.pdf
(7 pages)
3.ATTINY25_AUTOMOTIVE.pdf
(196 pages)
4.ATTINY45_AUTOMOTIVE.pdf
(25 pages)
Specifications of ATtiny45 Automotive
Flash (kbytes)
4 Kbytes
Pin Count
8
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
3
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
256
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY25_AUTOMOTIVE PDF datasheet #2
- ATTINY25_AUTOMOTIVE PDF datasheet #3
- ATTINY45_AUTOMOTIVE PDF datasheet #4
- Current page: 162 of 225
- Download datasheet (4Mb)
The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page
Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during
the entire Page Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to logical one at the same time as SPMEN, the next SPM instruction within
four clock cycles executes a page erase. The page address is taken from the high part of the
Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion
of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is
halted during the entire page erase operation.
• Bit 0 – SPMEN: Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If written to logical one
together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have
a special meaning (see description above). If only SPMEN is written, the following SPM
instruction will store the value in R1:R0 in the temporary page buffer addressed by the
Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion
of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During
page erase and page write, the SPMEN bit remains high until the operation is completed.
Writing any combination other than "10001", "01001", "00101", "00011", or "00001" in the
lower five bits will have no effect.
Atmel ATtiny24/44/84 [Preliminary]
162
7701E–AVR–02/11
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