ATtiny85 Automotive Atmel Corporation, ATtiny85 Automotive Datasheet - Page 89
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATtiny85 Automotive
Manufacturer Part Number
ATtiny85 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY25_AUTOMOTIVE.pdf
(7 pages)
3.ATTINY25_AUTOMOTIVE.pdf
(196 pages)
Specifications of ATtiny85 Automotive
Flash (kbytes)
8 Kbytes
Pin Count
8
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
3
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY25_AUTOMOTIVE PDF datasheet #2
- ATTINY25_AUTOMOTIVE PDF datasheet #3
- Current page: 89 of 225
- Download datasheet (4Mb)
13.9.6
13.9.7
7701E–AVR–02/11
TIMSK0 – Timer/Counter 0 Interrupt Mask Register
TIFR0 – Timer/Counter 0 Interrupt Flag Register
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bit 2- OCIE0B: Timer/Counter 0 Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the status register is set, the timer/coun-
ter 0 compare match B interrupt is enabled. The corresponding interrupt is executed if a
compare match in timer/counter occurs, i.e., when the OCF0B bit is set in the timer/counter 0
interrupt flag register (TIFR0).
• Bit 1– OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the status register is set, the timer/coun-
ter 0 compare match A interrupt is enabled. The corresponding interrupt is executed if a
compare match in timer/counter 0 occurs, i.e., when the OCF0A bit is set in the timer/counter
0 interrupt flag register (TIFR0).
• Bit 0– TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the status register is set, the timer/counter
0 overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in
timer/counter 0 occurs, i.e., when the TOV0 bit is set in the timer/counter 0 interrupt flag regis-
ter (TIFR0).
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bit 2– OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a compare match occurs between the timer/counter 0 and the data
in OCR0B, the output compare register 0 B. OCF0B is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logi-
cal one to the flag. When the I-bit in SREG, OCIE0B (timer/counter compare b match interrupt
enable), and OCF0B are set, the timer/counter compare match interrupt is executed.
• Bit 1– OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a compare match occurs between the timer/counter 0 and the data
in OCR0A, the output compare register 0 A. OCF0A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logi-
cal one to the flag. When the I-bit in SREG, OCIE0A (timer/counter 0 compare match interrupt
enable), and OCF0A are set, the timer/counter 0 compare match interrupt is executed.
Bit
0x39 (0x59)
Read/Write
Initial Value
Bit
0x38 (0x58)
Read/Write
Initial Value
R
R
7
–
0
7
–
0
R
6
–
0
R
6
–
0
Atmel ATtiny24/44/84 [Preliminary]
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
R
3
–
0
R
3
–
0
OCIE0B
OCF0B
R/W
R/W
2
0
2
0
OCIE0A
OCF0A
R/W
R/W
1
0
1
0
TOIE0
TOV0
R/W
R/W
0
0
0
0
TIMSK0
TIFR0
89
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