ATUC128D3 Atmel Corporation, ATUC128D3 Datasheet - Page 145

• Manufacturer Part Number: ATUC128D3
• Manufacturer: Atmel Corporation

Specifications of ATUC128D3

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 48 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 25
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 51
• Ext Interrupts: 51
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

If the on chip debug system is enabled, this instruction traps a software breakpoint for debugging. The breakpoint instruc-
tion will enter debug mode disabling all interrupts and exceptions. If the on chip debug system is not enabled, this
instruction will execute as a nop.
If no on chip debug system is implemented, this instruction will execute as a "NOP".
32000D–04/2011
BREAKPOINT – Software Debug Breakpoint
Architecture revision:
Architecture revision1 and higher.
Description
Operation:
I.
Syntax:
I.
Operands:
Status Flags:
Opcode:
Note:
15
1
if (SR[DM]==0)
else
breakpoint
None
Q:
V:
N:
Z:
C:
1
0
RSR_DBG ← SR;
RAR_DBG ← address of first non-completed instruction;
SR[R] ← 1;
SR[J] ← 1;
SR[D] ← 1;
SR[M2:M0] ← B’110;
SR[DM] ← 1;
SR[EM] ← 1;
SR[GM] ← 1;
PC ← EVBA+0x1C;
PC ← PC + 2;
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
1
0
1
9
1
8
0
0
1
1
4
1
3
0
0
AVR32
1
0
1
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