ATxmega256D3 Atmel Corporation, ATxmega256D3 Datasheet - Page 9

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ATxmega256D3

Manufacturer Part Number
ATxmega256D3
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega256D3

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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7. Memories
7.1
7.2
7.3
8134I–AVR–12/10
Features
Overview
In-System Programmable Flash Program Memory
The AVR architecture has two main memory spaces, the Program Memory and the Data Mem-
ory. In addition, the XMEGA D3 features an EEPROM Memory for non-volatile data storage. All
three memory spaces are linear and require no paging. The available memory size configura-
tions are shown in
memory signature row for calibration data, device identification, serial number etc.
Non-volatile memory spaces can be locked for further write or read/write operations. This pre-
vents unrestricted access to the application software.
The XMEGA D3 devices contains On-chip In-System Programmable Flash memory for program
storage, see
Flash address location is 16 bits.
The Program Flash memory space is divided into Application and Boot sections. Both sections
have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Pro-
Flash Program Memory
Data Memory
Production Signature Row Memory for factory programmed data
User Signature Row
– One linear address space
– In-System Programmable
– Self-Programming and Bootloader support
– Application Section for application code
– Application Table Section for application code or data storage
– Boot Section for application code or bootloader code
– Separate lock bits and protection for all sections
– One linear address space
– Single cycle access from CPU
– SRAM
– EEPROM
– I/O Memory
Byte and page accessible
Optional memory mapping for direct load and store
Configuration and Status registers for all peripherals and modules
16 bit-accessible General Purpose Register for global variables or flags
Device ID for each microcontroller device type
Serial number for each device
Oscillator calibration bytes
ADC and temperature sensor calibration data
One flash page in size
Can be read and written from software
Content is kept after chip erase
Figure 7-1 on page
”Ordering Information” on page
10. Since all AVR instructions are 16- or 32-bits wide, each
2. In addition each device has a Flash
XMEGA D3
9

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