ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 129
ATxmega64A4U
Manufacturer Part Number
ATxmega64A4U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A4U
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
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11.7.2
8331B–AVR–06/11
WINCTRL – Window Mode Control Register
Table 11-1.
• Bit 1 – ENABLE: Watchdog Enable
This bit enables the WDT. Clearing this bit disables the watchdog timer.
In order to change this bit, the CEN bit in
128
protection mechanism, For a detailed description, refer to
page
• Bit 0 – CEN: Watchdog Change Enable
This bit enables the ability to change the configuration of the
Register” on page
at the same time for the changes to take effect. This bit is protected by the configuration change
protection mechanism. For a detailed description, refer to
page
• Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 5:2 – WPER[3:0]: Watchdog Window Mode Timeout Period
These bits determine the closed window period as a number of 1kHz ULP oscillator cycles in
window mode operation. The typical different closed window periods are found in
Bit
+0x01
Read/Write
(unlocked)
Read/Write
(locked)
Initial Value
(x = fuse)
must be written to one at the same time. This bit is protected by the configuration change
PER[3:0]
12.
12.
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Watchdog timeout periods (Continued).
R
R
7
–
0
128. When writing a new value to this register, this bit must be written to one
R
R
6
–
0
Group Configuration
R/W
512CLK
R
X
5
1KCLK
2KCLK
4KCLK
8KCLK
R/W
”CTRL – Watchdog Timer Control Register” on page
R
4
X
WPER[3:0]
ATMEL CONFIDENTIAL
Atmel AVR XMEGA AU
R/W
R
X
3
”Configuration Change Protection” on
”Configuration Change Protection” on
R/W
”CTRL – Watchdog Timer Control
2
R
X
Typical Timeout Periods
WEN
R/W
R/W
X
1
Reserved
Reserved
Reserved
Reserved
Reserved
0.512s
1.0s
2.0s
4.0s
8.0s
WCEN
R/W
R/W
0
0
Table
WINCTRL
11-2.
129
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