SAM3U1E Atmel Corporation, SAM3U1E Datasheet - Page 28

• Manufacturer Part Number: SAM3U1E
• Manufacturer: Atmel Corporation

Specifications of SAM3U1E

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 57
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 5
• Twi (i2c): 2
• Uart: 5
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.6
7.7
28
DMA Controller
Peripheral DMA Controller
SAM3U Series
The DMA controller can handle the transfer between peripherals and memory and so receives
the triggers from the peripherals listed below. The hardware interface numbers are also given in
Table 7-4
Table 7-4.
•
•
•
•
• Acting as one Matrix Master
• Embeds 4 channels:
• Linked List support with Status Write Back operation at End of Transfer
• Word, HalfWord, Byte transfer support.
• Handles high speed transfer of SPI, SSC and HSMCI (peripheral to memory, memory to
• Memory to memory transfer
• Can be triggered by PWM and T/C which enables to generate waveforms though the
peripheral)
External Bus Interface
TIO Output of TImer
Handles data transfer between peripherals and memories
Nineteen channels
–
–
–
–
–
Low bus arbitration overhead
Next Pointer management for reducing interrupt latency requirement
Counter Channel 0
PWM Event Line 0
PWM Event Line 1
– 3 channels with 8 bytes/FIFO for Channel Buffering
– 1 channel with 32 bytes/FIFO for Channel Buffering
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
Instance name
Two for each USART
Two for the UART
Two for each Two Wire Interface
One for the PWM
One for each Analog-to-digital Converter
HSMCI
below.
SSC
SSC
SPI
SPI
DMA Controller
Transmit/Receive
Channel T/R
Transmit
Transmit
Receive
Receive
Trigger
Trigger
Trigger
DMA Channel HW interface
Number
6430ES–ATARM–22-Aug-11
0
1
2
3
4
5
6
7