SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 25

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.1
8.1.1
8.1.1.1
8.1.1.2
8.1.1.3
6257AS–ATARM–28-Feb-08
Embedded Memories
Internal Memories
Internal SRAM
Internal ROM
Internal Flash
The AT91SAM7L128/64 embeds a high-speed 4-Kbyte SRAM bank and a 2-Kbyte backup
SRAM bank. The backup SRAM is directly supplied on 1.8V-3.6V supply domain.
The 4-Kbyte Core SRAM is supplied by VDDCORE which is connected to the output of the volt-
age regulator.
After reset and until the Remap Command is performed, the 4-Kbyte Core SRAM is only acces-
sible at address 0x0020 0000. The 2-Kbyte Backup SRAM is accessible at address 0x0030
0000.
After remap, the 4-Kbyte Core SRAM also becomes available at address 0x0.
The user can see the 6 Kbytes of SRAM contiguously at address 0x002F F000.
The AT91SAM7L128/64 embeds an Internal ROM. The ROM is always mapped at address
0x0040 0000. The ROM contains the FFPI and SAM-BA program.
ROM size is 12 Kbytes.
At any time, the Flash is mapped to address 0x0010 0000.
A general purpose NVM (GPNVM1) bit is used to boot either on the ROM (default) or from the
Flash.
This GPNVM1 bit can be cleared or set respectively through the commands “Clear General-pur-
pose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface.
Setting the GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the
ROM. Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by
default.
• The AT91SAM7L128 features one bank of 128 Kbytes of Flash.
• The AT91SAM7L64 features one bank of 64 Kbytes of Flash.
AT91SAM7L128/64 Preliminary
25