SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 132

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug Interface
5.4
5.4.1
5-10
ARM7TDMI core clock domains
Clock switch during debug
The ARM7TDMI clocks are described in Clocks on page 5-2.
This section describes:
•
•
When the ARM7TDMI processor enters debug state, it switches automatically from
MCLK to DCLK, it then asserts DBGACK in the HIGH phase of MCLK. The switch
between the two clocks occurs on the next falling edge of MCLK. This is shown in
Figure 5-4.
The core is forced to use DCLK as the primary clock until debugging is complete. On
exit from debug, the core must be allowed to synchronize back to MCLK. This must be
done by the debugger in the following sequence:
1.
2.
The core now automatically resynchronizes back to MCLK and starts fetching
instructions from memory at MCLK speed.
See Exit from debug state on page B-26.
Clock switch during debug on page 5-10
Clock switch during test on page 5-11.
The final instruction of the debug sequence is shifted into the data bus scan chain
and clocked in by asserting DCLK.
RESTART is clocked into the TAP instruction register.
DBGACK
Copyright © 1994-2001. All rights reserved.
MCLK
DCLK
ECLK
Figure 5-4 Clock switching on entry to debug state
Multiplexer
switching point
ARM DDI 0029G