SAM7S128 Atmel Corporation, SAM7S128 Datasheet - Page 7
SAM7S128
Manufacturer Part Number
SAM7S128
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S128
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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ARM DDI 0029G
Chapter 7
Appendix A
Appendix B
6.14
6.15
6.16
6.17
6.18
6.19
6.20
AC and DC Parameters
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
7.23
7.24
7.25
Signal Description
A.1
Debug in Depth
B.1
B.2
B.3
B.4
B.5
B.6
B.7
Coprocessor data transfer from memory to coprocessor .......................... 6-21
Coprocessor data transfer from coprocessor to memory .......................... 6-23
Coprocessor register transfer, load from coprocessor .............................. 6-25
Coprocessor register transfer, store to coprocessor ................................. 6-26
Undefined instructions and coprocessor absent ....................................... 6-27
Unexecuted instructions ............................................................................ 6-28
Instruction speed summary ....................................................................... 6-29
Timing diagram information ......................................................................... 7-3
General timing ............................................................................................. 7-4
Address bus enable control ........................................................................ 7-6
Bidirectional data write cycle ....................................................................... 7-7
Bidirectional data read cycle ....................................................................... 7-8
Data bus control .......................................................................................... 7-9
Output 3-state timing ................................................................................. 7-10
Unidirectional data write cycle timing ........................................................ 7-11
Unidirectional data read cycle timing ........................................................ 7-12
Configuration pin timing ............................................................................ 7-13
Coprocessor timing ................................................................................... 7-14
Exception timing ........................................................................................ 7-15
Synchronous interrupt timing .................................................................... 7-16
Debug timing ............................................................................................. 7-17
Debug communications channel output timing ......................................... 7-19
Breakpoint timing ...................................................................................... 7-20
Test clock and external clock timing ......................................................... 7-21
Memory clock timing ................................................................................. 7-22
Boundary scan general timing .................................................................. 7-23
Reset period timing ................................................................................... 7-24
Output enable and disable times .............................................................. 7-25
Address latch enable control ..................................................................... 7-26
Address pipeline control timing ................................................................. 7-27
Notes on AC Parameters .......................................................................... 7-28
DC parameters .......................................................................................... 7-34
Signal description ........................................................................................ A-2
Scan chains and JTAG interface ................................................................ B-3
Resetting the TAP controller ....................................................................... B-6
Pullup resistors ........................................................................................... B-7
Instruction register ...................................................................................... B-8
Public instructions ....................................................................................... B-9
Test data registers .................................................................................... B-14
The ARM7TDMI core clocks ..................................................................... B-22
Copyright © 1994-2001. All rights reserved.
Contents
vii
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