SAM7S32 Atmel Corporation, SAM7S32 Datasheet - Page 75
SAM7S32
Manufacturer Part Number
SAM7S32
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S32
Flash (kbytes)
32 Kbytes
Pin Count
48
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
21
Ext Interrupts
21
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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3.3.1
ARM DDI 0029G
Nonsequential cycles
Bus cycle types are encoded on the nMREQ and SEQ signals as listed in Table 3-1.
A memory controller for the ARM7TDMI processor must commit to a memory access
only on an N-cycle or an S-cycle.
A nonsequential cycle is the simplest form of bus cycle, and occurs when the processor
requests a transfer to or from an address that is unrelated to the address used in the
preceding cycle. The memory controller must initiate a memory access to satisfy this
request.
The address class and (nMREQ and SEQ) signals that comprise an N-cycle are
broadcast on the bus. At the end of the next bus cycle the data is transferred between the
CPU and the memory. It is not uncommon for a memory system to require a longer
access time (extending the clock cycle) for nonsequential accesses. This is to allow time
for full address decoding or to latch both a row and column address into DRAM. This
is illustrated in Figure 3-2 on page 3-6.
In Figure 3-2 on page 3-6, nMREQ and SEQ are highlighted where they are valid to
indicate the N-cycle.
Note
Copyright © 1994-2001. All rights reserved.
nMREQ
0
0
1
1
SEQ
0
1
0
1
Bus cycle type
N-cycle
S-cycle
I-cycle
C-cycle
Description
Nonsequential cycle
Sequential cycle
Internal cycle
Coprocessor register transfer cycle
Table 3-1 Bus cycle types
Memory Interface
3-5
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