SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 88
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SAM7SE256
Manufacturer Part Number
SAM7SE256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7SE256
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
48 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
88
Ext Interrupts
88
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Memory Interface
3-18
Unidirectional data bus
When BUSEN is HIGH, all instructions and input data are presented on the input data
bus, DIN[31:0]. The timing of this data is similar to that of the bidirectional bus when
in input mode. Data must be set up and held to the falling edge of MCLK. For the exact
timing requirements refer to Chapter 7 AC and DC Parameters.
In this configuration, all output data is presented on DOUT[31:0]. The value on this bus
only changes when the processor performs a store cycle. Again, the timing of the data
is similar to that of the bidirectional data bus. The value on DOUT[31:0] changes after
the falling edge of MCLK.
The bus timing of a read-write-read cycle combination is shown in Figure 3-13.
When the unidirectional data buses are being used, and BUSEN is HIGH, the
bidirectional bus, D[31:0], must be left unconnected.
The unidirectional buses are typically used internally in ASIC embedded applications.
Externally, most systems still require a bidirectional data bus to interface to external
memory. Figure 3-14 on page 3-19 shows how you can join the unidirectional buses up
at the pads of an ASIC to connect to an external bidirectional bus.
Copyright © 1994-2001. All rights reserved.
DOUT[31:0]
DIN[31:0]
D[31:0]
MCLK
read cycle
D[31:0]
MCLK
D1
D1
Figure 3-13 Unidirectional bus timing
write cycle
Figure 3-12 Bidirectional bus timing
read cycle write cycle read cycle
Dout
read cycle
Dout
ARM DDI 0029G
D2
D2
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