SAM7X128 Atmel Corporation, SAM7X128 Datasheet - Page 285
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
SAM7X128
Manufacturer Part Number
SAM7X128
Description
Manufacturer
Atmel Corporation
Specifications of SAM7X128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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29.5.4
Figure 29-9. Master Read with Multiple Data Bytes
6120I–ATARM–06-Apr-11
TXCOMP
RXRDY
TWD
Master Receiver Mode
S
Write START Bit
DADR
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See
performed, with or without internal address (IADR), the STOP bit must be set after the next-to-
last data received. See
Figure 29-8. Master Read with One Data Byte
R
A
TXCOMP
DATA n
RXRDY
TWD
Figure
Read RHR
A
S
DATA n
Write START &
29-9. For Internal Address usage see
DATA (n+1)
STOP Bit
DADR
A
DATA (n+1)
Read RHR
R
DATA (n+m)-1
Figure
A
29-8. When a multiple data byte read is
SAM7X512/256/128
DATA
DATA (n+m)-1
A
Read RHR
after next-to-last data read
DATA (n+m)
Read RHR
Section
Write STOP Bit
N
Figure
P
29.5.5.
N
29-9. When the
DATA (n+m)
Read RHR
P
285
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