SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 49
SAM7X256
Manufacturer Part Number
SAM7X256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7X256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
62
Ext Interrupts
62
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
3
Can
1
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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12.5.4.1
6120I–ATARM–06-Apr-11
JTAG Boundary-scan Register
with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1
JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per-
formed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
The Boundary-scan Register (BSR) contains 187 bits that correspond to active pins and associ-
ated control signals.
Each SAM7X input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit con-
tains data that can be forced on the pad. The INPUT bit facilitates the observability of data
applied to the pad. The CONTROL bit selects the direction of the pad.
Table 12-2.
Number
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
Bit
SAM7X JTAG Boundary Scan Register
PA2/SCK0/SPI1_NPCS1
PA3/RTS0/SPI1_NPCS2
PA4/CTS0/SPI1_NPCS3
PA30/IRQ0/PCK2
PA0/RXD0
PA5/RXD1
Pin Name
PA1/TXD0
PA6/TXD1
Pin Type
SAM7X512/256/128
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
Associated BSR
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Cells
49
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