SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 156

• Manufacturer Part Number: SAM7X256
• Manufacturer: Atmel Corporation

Specifications of SAM7X256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Timings
6.8
6-14
Store register
Cycle
1
2
The first cycle of a store register instruction is similar to the first cycle of load register
instruction. During the second cycle the base modification is performed, and at the same
time the data is written to memory. There is no third cycle.
The cycle timings are listed in Table 6-11 where:
•
•
•
Address
pc+2L
alu
pc+3L
c represents the current processor mode:
—
—
d=0 if the T bit has been specified in the instruction (such as LDRT) and d=c at
all other times.
s represents the size of the data transfer shown by MAS[1:0] (see Table 6-10 on
page 6-13).
Copyright © 1994-2001. All rights reserved.
c=0 for User mode
c=1 for all other modes
MAS[1:0]
i
s
nRW
0
1
Table 6-11 Store register instruction cycle operations
Data
(pc+2L)
Rd
nMREQ
0
0
SEQ
0
0
nOPC
0
1
ARM DDI 0029G
nTRANS
c
d