SAM7XC128 Atmel Corporation, SAM7XC128 Datasheet - Page 30

• Manufacturer Part Number: SAM7XC128
• Manufacturer: Atmel Corporation

Specifications of SAM7XC128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Resolution (bits): No
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 32
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

9.5
9.6
9.7
9.8
30
Debug Unit
Periodic Interval Timer
Watchdog Timer
Real-time Timer
AT91SAM7XC512/256/128
• Vectoring
• Protect Mode
• Fast Forcing
• General Interrupt Mask
• Comprises:
• Two-pin UART
• Debug Communication Channel Support
• Chip ID Registers
• 20-bit programmable counter plus 12-bit interval counter
• 12-bit key-protected Programmable Counter running on prescaled SLCK
• Provides reset or interrupt signals to the system
• Counter may be stopped while the processor is in debug state or in idle mode
• 32-bit free-running counter with alarm running on prescaled SLCK
– Higher priority interrupts can be served during service of lower priority interrupt
– Optimizes interrupt service routine branch and execution
– One 32-bit vector register per interrupt source
– Interrupt vector register reads the corresponding current interrupt vector
– Easy debugging by preventing automatic operations
– Permits redirecting any interrupt source on the fast interrupt
– Provides processor synchronization on events without triggering an interrupt
– One two-pin UART
– One Interface for the Debug Communication Channel (DCC) support
– One set of Chip ID Registers
– One Interface providing ICE Access Prevention
– USART-compatible User Interface
– Programmable Baud Rate Generator
– Parity, Framing and Overrun Error
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Offers visibility of COMMRX and COMMTX signals from the ARM Processor
– Identification of the device revision, sizes of the embedded memories, set of
– Chip ID is 0x271C 0A40 (VERSION 0) for AT91SAM7XC512
– Chip ID is 0x271B 0940 (VERSION 0) for AT91SAM7XC256
– Chip ID is 0x271A 0740 (VERSION 0) for AT91SAM7XC128
peripherals
6209DS–ATARM–17-Feb-09