SAM9G15 Atmel Corporation, SAM9G15 Datasheet
SAM9G15
Specifications of SAM9G15
Related parts for SAM9G15
SAM9G15 Summary of contents
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... Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input – Individually Programmable Open-drain, Pull-up and pull-down resistor, Synchronous Output • Package • 217-ball BGA, pitch 0.8 mm ® Processor running 400 MHz @ 1.0V +/- 10% AT91SAM ARM-based Embedded MPU SAM9G15 11052C–ATARM–21-Nov-11 ...
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... Description The SAM9G15, based on the ARM926EJ-S processor, runs at 400 MHz and integrates a rich set of peripherals to support embedded industrial applications that require advanced user inter- faces and high-speed communication. The SAM9G15 features a graphics LCD controller with 4-layer overlay and 2D acceleration (pic- ture-in-picture, alpha-blending, scaling, rotation, color conversion), and a 10-bit ADC that supports 4/5-wire resistive touchscreen panels ...
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... Block Diagram Figure 2-1. SAM9G15 Block Diagram 11052C–ATARM–21-Nov-11 PIO PIO SAM9G15 3 ...
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... Fast Interrupt Input PA0-PA31 Parallel IO Controller A PB0-PB18 Parallel IO Controller B PC0-PC31 Parallel IO Controller C PD0-PD21 Parallel IO Controller D SAM9G15 4 gives details on the signal name classified by peripheral. Clocks, Oscillators and PLLs Shutdown, Wakeup Logic ICE and JTAG Reset/Test Debug Unit - DBGU Advanced Interrupt Controller - AIC ...
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... Multimedia Card 0 Slot A Data MCI1_DA0-MCI1_DA3 Multimedia Card 1 Slot A Data 11052C–ATARM–21-Nov-11 External Bus Interface - EBI Static Memory Controller - SMC NAND Flash Support DDR2/SDRAM/LPDDR Controller High Speed MultiMedia Card Interface - HSMCI0-1 SAM9G15 Type Active Level I/O I/O Output Input Low Output Low ...
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... SPI Peripheral Chip Select TWDx Two-wire Serial Data TWCKx Two-wire Serial Clock PWM0-PWM3 Pulse Width Modulation Output SAM9G15 6 Universal Asynchronous Receiver Transmitter - UARTx Synchronous Serial Controller - SSC Timer/Counter - TCx x=0..5 Serial Peripheral Interface - SPIx Two-Wire Interface -TWIx Pulse Width Modulation Controller- PWMC ...
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... Soft Modem Signal DIBP Soft Modem Signal 11052C–ATARM–21-Nov-11 USB Host High Speed Port - UHPHS USB Device High Speed Port - UDPHS LCD Controller - LCDC Analog-to-Digital Converter - ADC Soft Modem - SMD SAM9G15 Type Active Level Analog Analog Analog Analog Analog Analog ...
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... Package and Pinout The SAM9G15 is available in a 217-ball BGA package. 4.1 Overview of the 217-ball BGA Package Figure 4-1 Figure 4-1. SAM9G15 8 shows the orientation of the 217-ball BGA Package. Orientation of the 217-ball BGA Package ...
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... EBI_CLK RSTJTAG SYSC VBG 11052C–ATARM–21-Nov-11 SAM9G15 I/O Type Description Voltage Range Analog 1.65-3.6V 1.65-3.6V 1.65-3.6V 3.0-3.6V I 1.65-1.95V, 3.0- 3.6V 1.65-1.95V, 3.0- 3.6V 1.65-1.95V, 3.0- 3.6V 3.0-3.6V 1.65-3.6V 0.9-1.1V I 3.0-3.6V I/O 3.0-3.6V I/O 1.65-3.6V I/O 3.0-3.6V I/O SAM9G15 I/O Type Assignment and Frequency I/O Frequency Charge Load Output (MHz) (pF) Current 16mA 40mA (peak) 50 (3.3V) 133 30 (1.8V) 50 (3.3V (1.8V) 133 0.25 10 0.25 10 ...
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... Indicates whether the signal is input or output state. • “PU”/”PD” Indicates whether Pull-Up, Pull-Down or nothing is enabled. • “ST” Indicates if Schmitt Trigger is enabled. Note: SAM9G15 10 SAM9G15 I/O Type Assignment and Frequency (Continued) I/O Frequency Charge Load (MHz) (pF 480 10 ...
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... I/O TCLK0 I/O TCLK1 I/O TCLK2 I/O TIOB0 I/O TIOB1 I/O TIOB2 I/O TWD0 I/O TWCK0 PB0 I/O PB1 I/O PB2 I/O PB3 I/O PB4 I/O PB5 I/O PB6 I/O AD7 I PB7 I/O AD8 I SAM9G15 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal O SPI1_NPCS1 O I SPI0_NPCS2 O O MCI1_DA1 I/O I MCI1_DA2 I/O I/O MCI1_DA3 I SPI0_NPCS1 O I SPI1_NPCS0 I I/O MCI1_DA0 I/O I/O MCI1_CDA ...
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... VDDIOP1 GPIO PC24 M2 VDDIOP1 GPIO PC25 P2 VDDIOP1 GPIO PC26 M1 VDDIOP1 GPIO PC27 K4 VDDIOP1 GPIO PC28 N1 VDDIOP1 GPIO_CLK PC29 R2 VDDIOP1 GPIO_CLK2 PC30 N2 VDDIOP1 GPIO PC31 SAM9G15 12 Primary Alternate PIO Peripheral A Dir Signal Dir Signal I/O AD9 I I/O AD10 I I/O AD11 I I/O AD0 I I/O AD1 I I/O AD2 I I/O AD3 I I/O AD4 ...
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... D23 I/O D24 I/O D25 I/O D26 I/O D27 I/O D28 I/O D29 I/O D30 I/O D31 SAM9G15 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal A20 O O A23 O O A24 O O A25 ...
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... A16 B17 VDDIOM EBI_O A17 E15 VDDIOM EBI_O A18 E14 VDDIOM EBI_O A19 B9 VDDIOM EBI_O NCS0 B8 VDDIOM EBI_O NCS1 D9 VDDIOM EBI_O NRD C9 VDDIOM EBI_O NWR0 C7 VDDIOM EBI_O NWR1 SAM9G15 14 Primary Alternate PIO Peripheral A Dir Signal Dir Signal I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O NBS0 O NBS2/DQM NWR2 ...
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... I/O I/O I BMS I I TST I TCK I TDI I TDO O TMS XIN I O SAM9G15 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal Reset State Signal, Dir, PU, Dir PD ...
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... Power Considerations 5.1 Power Supplies The SAM9G15 has several types of power supply pins. Table 5-1. SAM9G15 Power Supplies Name Voltage Range, nominal VDDCORE 0.9-1.1V, 1.0V 1.65-1.95V, 1.8V VDDIOM 3.0-3.6V, 3.3V 1.65-1.95V, 1.8V VDDNF 3.0-3.6V, 3.3V VDDIOP0 1.65-3.6V VDDIOP1 1.65-3.6V VDDBU 1.65-3.6V VDDUTMIC 0.9-1.1V, 1.0V VDDUTMII 3.0-3.6V, 3.3V VDDPLLA 0.9-1.1V, 1.0V VDDOSC 1.65-3.6V VDDANA 3.0-3.6V, 3.3V Note: 1. Refer to Table 4-2 for more details. SAM9G15 16 Powers ARM core, internal memories, internal peripherals and part of the system controller ...
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... Memories Figure 6-1. SAM9G15 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1 DDR2/LPDDR SDR/LPSDR 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 0x4000 0000 EBI Chip Select 3 ...
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... Embedded Memories 6.2.1 Internal SRAM The SAM9G15 embeds a total of 32 Kbytes of high-speed SRAM. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. After Remap, the SRAM also becomes available at address 0x0. 6.2.2 Internal ROM The SAM9G15 embeds an Internal ROM, which contains the SAM-BA At any time, the ROM is mapped at address 0x0010 0000 ...
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... SDRAM Power-up Initialization by Software • CAS Latency Supported • Auto Precharge Command Not Used • SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported – Clock Frequency Change in Precharge Power-down Mode Not Supported 11052C–ATARM–21-Nov-11 Average Latency of Transactions) SAM9G15 19 ...
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... System Controller can be addressed from a single pointer by using the stan- dard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KBytes. Figure 7-1 on page 21 Figure 6-1 on page 17 peripherals. SAM9G15 20 shows the System Controller block diagram. shows the mapping of the User Interface of the System Controller 11052C–ATARM–21-Nov-11 ...
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... Figure 7-1. SAM9G15 System Controller Block Diagram periph_irq[2..30] pit_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP XIN32 SLOW CLOCK XOUT32 OSC XIN 12MHz MAIN OSC XOUT UPLL PLLA periph_nreset periph_nreset periph_clk[2..3] PA0-PA31 PB0-PB18 ...
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... Chip ID: 0x819A_05A1 • Chip ID Extension: 0 • JTAG ID: 0x05B2_F03F • ARM926 TAP ID: 0x0792_603F 7.2 Backup Section The SAM9G15 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • Real Time Counter (RTC) • Shutdown Controller • 4 Backup Registers • Slow Clock Control Register (SCKCR) • ...
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... Figure 6-1, the Peripherals are mapped in the upper 256 Mbytes of the address defines the Peripheral Identifiers of the SAM9G15. A peripheral identifier is required Peripheral Identifiers Instance Name Instance Description AIC Advanced Interrupt Controller SYS System Controller Interrupt ...
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... Peripheral Signal Multiplexing on I/O Lines The SAM9G15 features 4 PIO controllers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls 32 lines, 19 lines, 32 lines and 22 lines respectively for PIOA, PIOB, PIOC and PIOD. Each line can be assigned to one of three peripheral functions ...
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... Critical-word First Cache Refilling 11052C–ATARM–21-Nov-11 ™ integer core ™ ® Based on ARM Architecture v5TEJ with Jazelle Technology ® High-performance 32-bit Instruction Set ® High Code Density 16-bit Instruction Set ® 8-bit Instruction Set SAM9G15 ™ family of general-purpose microproces- 25 ...
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... Separate AMBA AHB Buses for Both the 32-bit Data Interface and the 32-bit • Bus Interface Unit – Arbitrates and Schedules AHB Requests – Enables Multi-layer AHB to be Implemented – Increases Overall Bus Bandwidth – Makes System Architecture Mode Flexible SAM9G15 26 Instructions Interface 11052C–ATARM–21-Nov-11 ...
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... External Coprocessor Interface ARM9EJ-S Processor Core Read Data Data Instruction Address MMU Instruction Data TLB TLB Data Address AHB Interface and Write Buffer AMBA AHB SAM9G15 ETM9 Trace Port Interface Instruction Fetches Address ITCM Interface Instruction TCM Instruction Address Instruction Cache 27 ...
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... ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. SAM9G15 28 11052C–ATARM–21-Nov-11 ...
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... R10 R10 R11 R11 Interrupt Mode Fast Interrupt Mode R10 R10 R11 R11 SAM9G15 R8_FIQ R9_FIQ R10_FIQ R11_FIQ 29 ...
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... For more details, refer to ARM Software Development Kit. The Thumb state register set is a subset of the ARM state set. The programmer has direct access to: • Eight general-purpose registers r0-r7 • Stack pointer, SP • Link register, LR (ARM r14) • PC • CPSR SAM9G15 30 Abort Mode Undefined Mode R12 R12 R13_ABORT R13_UNDEF ...
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... Reserved Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than shows the status register format, where: SAM9G15 0 Mode Mode bits Thumb state bit FIQ disable IRQ disable 31 ...
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... Execute stage in the pipeline. If the instruction is not executed, for example because a branch occurs while the pipeline, the abort does not take place. SAM9G15 32 into LR (current PC(r15 depending on the exception). ...
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... Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte SAM9G15 Mnemonic Operation MVN Move Not ADC Add with Carry SBC Subtract with Carry RSC Reverse Subtract with Carry ...
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... The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: • Branch instructions • Data processing instructions • Load and Store instructions SAM9G15 34 ARM Instruction Mnemonic List (Continued) Operation Load Register Byte with Translation ...
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... Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack Conditional Branch SAM9G15 Mnemonic Operation MVN Move Not ADC Add with Carry SBC Subtract with Carry CMN Compare Negated ...
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... Table 9-5. Register Notes: SAM9G15 36 CP15 Registers Name ( Code (1) 0 Cache type (1) 0 TCM status 1 Control 2 Translation Table Base 3 Domain Access Control 4 Reserved (1) 5 Data fault Status (1) 5 Instruction fault status 6 Fault Address 7 Cache Operations 8 TLB operations (2) 9 cache lockdown 9 TCM region ...
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... Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM. 11052C–ATARM–21-Nov-11 MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2 SAM9G15 CRn CRm ...
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... Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modi- SAM9G15 38 Mapping Details Mapping Size Access Permission By ...
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... This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so 11052C–ATARM–21-Nov-11 SAM9G15 39 ...
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... The Write Buffer can hold words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. SAM9G15 40 11052C–ATARM–21-Nov-11 ...
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... The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. 11052C–ATARM–21-Nov-11 SAM9G15 41 ...
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... The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. SAM9G15 42 Single transfer of word, half word, or byte: • data write (NCNB, NCB, WT that has missed in DCache) • ...
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... Debug and Test 10.1 Description The SAM9G15 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as down- loading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communica- tion Channel ...
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... Block Diagram Figure 10-1. Debug and Test Block Diagram TAP: Test Access Port SAM9G15 44 ICE/JTAG Boundary TAP Port ARM9EJ-S ICE-RT ARM926EJ-S DMA DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR Reset and TST Test DTXD DRXD 11052C–ATARM–21-Nov-11 ...
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... Trace Port interface utilizing the ICE/JTAG interface. Figure 10-2. Application Debug and Trace Environment Example 11052C–ATARM–21-Nov-11 shows a complete debug environment example. The ICE/JTAG interface is used for ICE/JTAG Interface ICE/JTAG Connector RS232 SAM9 Connector SAM9-based Application Board SAM9G15 Host Debugger Terminal 45 ...
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... Figure 10-3 ter. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 10-3. Application Test Environment Example SAM9G15 46 shows a test environment example. Test vectors are sent and interpreted by the tes- Test Adaptor ...
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... ICE and JTAG Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select Returned Test Clock JTAG Selection Debug Unit Debug Receive Data Debug Transmit Data SAM9G15 Type Active Level Input/Output Low Input High Input Low Input Input ...
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... TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. SAM9G15 48 ™ is supported via the ICE/JTAG port connected to a ...
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... ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant not possible to switch directly between JTAG and ICE operations. A chip reset must be per- formed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 11052C–ATARM–21-Nov-11 SAM9G15 49 ...
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... VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B2F • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B2_F03F. SAM9G15 PART NUMBER 13 12 ...
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... XTal or external clock frequency detection • attempt to retrieve a valid code from external non-volatile memories (NVM) • execution of a monitor called SAM-BA Monitor, in case no valid application has been found on any NVM 11052C–ATARM–21-Nov-11 (Section 11.1 “ROM Code”) SAM9G15 51 ...
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... MHz external clock or crystal frequency running at 12 MHz is found, then the PLLA is configured to allow communication on the USB link for the SAM-BA Monitor; else the Main Clock is switched to the internal 12 MHz Fast RC, but USB will not be activated. SAM9G15 52 Figure Chip Setup ...
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... BSCR Value. Boot Sequence Register Values NAND SPI0 NPCS0 SDCard Flash SAM9G15 Figure 11-2 “NVM Bootloader SAM-BA SPI0 NPCS1 TWI EEPROM Monitor ...
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... Setup SPI0 CS0 Flash Boot No SD Card Boot No NAND Flash Boot No SPI0 CS1 Flash Boot No TWI EEPROM Boot No SAM-BA Monitor SAM9G15 Copy from SPI Flash to SRAM Y es Copy from SD Card to SRAM Y es Copy from NAND Flash to SRAM Y es Copy from ...
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... Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals. Perform the REMAP and set the jump to the downloaded application End SAM9G15 Restore the reset values for the peripherals and Jump to next boot solution 55 ...
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... Figure 11-6. B Opcode Unconditional instruction: 0xE for bits Load PC with PC relative addressing instruction: – 0xF – I==0 (12-bit immediate value) – P==1 (pre-indexed) – U offset added (U==1) or subtracted (U==0) – W==1 SAM9G15 56 0x0000_0000 Internal ROM 0x0010_0000 Internal ROM 0x0030_0000 Internal SRAM ...
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... NAND Flash, or • through the ONFI parameters for ONFI compliant memories. 11052C–ATARM–21-Nov-11 Size of the code to download in bytes ea000006 B 0x20 eafffffe B 0x04 ea00002f B _main eafffffe B 0x0c eafffffe B 0x10 <- Code size = 4660 bytes 00001234 B 0x14 eafffffe B 0x18 SAM9G15 0 57 ...
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... Figure 11-8. Boot NAND Flash Download SAM9G15 58 Start Initialize NAND Flash interface Send Reset command No First page contains valid header Yes Read NAND Flash and PMECC parameters Read NAND Flash and PMECC parameters from the header Copy the valid code from external NVM to internal SRAM. ...
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... If the header is valid, the Boot Program will continue with the detection of valid code. 11052C–ATARM–21-Nov- eccOffset SAM9G15 26 25 eccOffset 18 17 sectorSize 10 9 spareSize 2 1 nbSectorPerPage ...
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... PMECC base address, pPMERRLOC : pointer to the PMERRLOC base address, PMECC_desc : pointer to the PMECC descriptor, PMECC_status : the status returned by the read of PMECCISR register; SAM9G15 60 Booting on 16-bit NAND Flash is not possible, only 8-bit NAND Flash memories are supported. AT91PS_PMERRLOC pPMERRLOC, ...
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... TT_MAX + 1]; /* polynom order */ short lmu[TT_MAX + 1]; SAM9G15 61 ...
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... SPI DataFlash. It uses only one valid code detection: analysis of ARM exception vectors. The SPI Flash read is done by means of a Continuous Read command from address 0x0. This command is 0xE8 for DataFlash and 0x0B for Serial Flash devices. SAM9G15 62 0x0010_0000 ROM Code ...
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... Mbit 2 Mbits 4 Mbits 8 Mbits 16 Mbits 32 Mbits 64 Mbits 2 C-compatible TWI EEPROM memories using 7-bit device contains a list of pins that are driven during the boot program execution. These pins SAM9G15 Page Size (bytes) Number of Pages 264 512 264 1024 264 2048 264 4096 ...
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... Check if USB Device enumeration has occurred – Check if characters have been received on the DBGU Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as listed in SAM9G15 64 PIO Driven during Boot Program Execution Peripheral EBI CS3 SMC ...
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... Address,# write a word Address, Value# read a word Address,# send a file Address,# receive a file Address, NbOfBytes# go Address# display version No argument SAM9G15 No No Character(s) received on DBGU ? Yes Run monitor Wait for command on the DBGU link Example N# T# O200001,CA# o200001,# H200002,CAFE# ...
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... CRC16 Figure 11-11 SAM9G15 66 There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. ...
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... Windows 98SE to Windows XP Handled Standard Requests Definition Returns the current device configuration value. Sets the device address for all future device access. Sets the device configuration. Returns the current device configuration value. SAM9G15 Device ® . The CDC document, available at 67 ...
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... Endpoint 64-byte Bulk OUT endpoint and endpoint 64-byte Bulk IN endpoint. SAM- BA Boot commands are sent by the host through endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. SAM9G15 68 Handled Standard Requests (Continued) Definition Returns status for the specified recipient ...
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... This register is programmable with user programs or SAM-BA and key-protected. 12.2 Embedded Characteristics • VDDBU powered • Product-dependent order 12.3 Boot Sequence Controller Registers (BSC) User Interface Table 12-1. Register Mapping Offset Register 0x0 Boot Sequence Configuration Register 11052C–ATARM–21-Nov-11 Name BSC_CR SAM9G15 Access Reset Read-write – 69 ...
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... Read-write Factory Value:0x0000_0000 • BOOTx: Boot media sequence Is defined in the product-dependent ROM code. • BOOTKEY 0xB5 (VALID): valid boot key To avoid spurious writing, this key is necessary for write accesses. SAM9G15 BOOTKEY BOOT BOOT 5 ...
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... Interrupt Vector Register Reads the Corresponding Current Interrupt Vector • Protect Mode – Easy Debugging by Preventing Automatic Operations when Protect Models Are • Fast Forcing – Permits Redirecting any Normal Interrupt Source to the Fast Interrupt of the 11052C–ATARM–21-Nov-11 External Interrupts External Sources Enabled Processor SAM9G15 71 ...
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... General Interrupt Mask – Provides Processor Synchronization on Events Without Triggering an Interrupt • Write Protected Registers 13.3 Block Diagram Figure 13-1. Block Diagram 13.4 Application Block Diagram Figure 13-2. Description of the Application Block SAM9G15 72 FIQ AIC IRQ0-IRQn Up to Thirty-two Sources Embedded PeripheralEE Embedded Peripheral Embedded ...
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... IRQ0-IRQn PIOIRQ Internal Source Input Stage Embedded Peripherals I/O Line Description Pin Description Fast Interrupt Interrupt 0 - Interrupt n I/O Lines Signal AIC FIQ AIC IRQ SAM9G15 ARM Processor Fast nFIQ Interrupt Controller nIRQ Interrupt Fast Processor Priority Forcing Clock Controller Power Management Controller User Interface ...
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... Interrupt Clearing and Setting All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clear- ing or setting interrupt sources programmed in level-sensitive mode has no effect. SAM9G15 74 11052C–ATARM–21-Nov-11 ...
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... AIC_ISCR AIC_ICCR 11052C–ATARM–21-Nov-11 (See “Priority Controller” on page AIC_SMRI (SRCTYPE) Level/ AIC_IPR Edge Edge Detector Set Clear 78.) The automatic clear reduces See “Fast Forcing” on “Priority Controller” on page AIC_IMR Fast Interrupt Controller or Priority Controller AIC_IECR FF AIC_IDCR SAM9G15 75 ...
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... Figure 13-5. External Interrupt Source Input Stage High/Low Source i Detector Set AIC_ISCR AIC_ICCR 13.8.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including: • The time the software masks the interrupts. SAM9G15 76 AIC_SMRi SRCTYPE Level/ AIC_IPR Edge Pos./Neg. Edge Clear AIC_IMR Fast Interrupt Controller ...
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... Edge) IRQ or FIQ (Negative Edge) nIRQ Maximum IRQ Latency = 4 Cycles nFIQ Maximum FIQ Latency = 4 Cycles External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles SAM9G15 77 ...
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... The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority interrupt condition happens (or is pending) during the interrupt treatment in SAM9G15 78 Internal Interrupt Edge Triggered Source ...
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... This section gives an overview of the fast interrupt handling sequence when using the AIC assumed that the programmer understands the architecture of the ARM processor, and espe- cially the processor interrupt modes and the associated status bits assumed that: 11052C–ATARM–21-Nov-11 PC,[PC,# -&F20] SAM9G15 79 ...
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... PC. This has the effect of returning from the interrupt to whatever was being exe- cuted before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq. Note: SAM9G15 80 priority. The current level is the priority level of the current interrupt. must be read in order to de-assert nIRQ. ...
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... ARM core adjusts R14_fiq, decre- menting it by four. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automati- 11052C–ATARM–21-Nov-11 PC,[PC,# -&F20] SAM9G15 81 ...
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... The read of the FVR does not clear the Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). SAM9G15 82 The “F” bit in SPSR is significant set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted ...
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... AIC_IPR Input Stage Automatic Clear AIC_IMR Read FVR if Fast Forcing is disabled on Sources 1 to 31. AIC_FFSR AIC_IPR Input Stage AIC_IMR Automatic Clear Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n. SAM9G15 nFIQ Priority Manager nIRQ 83 ...
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... Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt strongly recommended to use this mask with caution. SAM9G15 84 11052C–ATARM–21-Nov-11 ...
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... Source Vector Register” on page 88 • “AIC Spurious Interrupt Vector Register” on page 99 • “AIC Debug Control Register” on page 100 11052C–ATARM–21-Nov-11 (AIC_WPSR) is set and the WPVSRC field indicates in which register SAM9G15 AIC Write Protect Mode Register AIC Write 85 ...
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... The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. 2. PID2...PID31 bit fields refer to the identifiers as defined in the Peripheral Identifiers Section of the product datasheet. SAM9G15 86 Register Source Mode Register 0 ...
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... Positive edge triggered for internal source Negative edge triggered for external source High level Sensitive for internal source High level Sensitive for external source Positive edge triggered for internal source Positive edge triggered for external source SAM9G15 – – – ...
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... Reset: 0x0 This register can only be written if the WPEN bit is cleared in • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source. SAM9G15 VECTOR VECTOR ...
Page 89
... The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. 11052C–ATARM–21-Nov- IRQV IRQV IRQV IRQV SAM9G15 ...
Page 90
... FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU. SAM9G15 FIQV ...
Page 91
... The Interrupt Status Register returns the current interrupt source number. 11052C–ATARM–21-Nov- – – – – – – – – – – SAM9G15 – – – – – – – – – IRQID 91 ...
Page 92
... Read-only Reset: 0x0 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Mask 0 = Corresponding interrupt is disabled Corresponding interrupt is enabled. SAM9G15 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 5 4 ...
Page 93
... SAM9G15 – – – – – – – – – – NIRQ NFIQ 93 ...
Page 94
... Access: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Enable effect Enables corresponding interrupt. SAM9G15 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 ...
Page 95
... No effect Disables corresponding interrupt. 11052C–ATARM–21-Nov- PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9G15 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS FIQ 95 ...
Page 96
... Access: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Clear effect Clears corresponding interrupt. SAM9G15 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 ...
Page 97
... No effect Sets corresponding interrupt. 11052C–ATARM–21-Nov- PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9G15 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS FIQ 97 ...
Page 98
... The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. SAM9G15 – – ...
Page 99
... The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt. 11052C–ATARM–21-Nov- SIVR SIVR SIVR SIVR AIC Write Protect Mode Register SAM9G15 ...
Page 100
... PROT: Protection Mode 0 = The Protection Mode is disabled The Protection Mode is enabled. • GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC The nIRQ and nFIQ lines are tied to their inactive state. SAM9G15 100 – – ...
Page 101
... Enables the fast forcing feature on the corresponding interrupt. 11052C–ATARM–21-Nov- PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9G15 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS – 101 ...
Page 102
... PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Disable effect Disables the Fast Forcing feature on the corresponding interrupt. SAM9G15 102 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 ...
Page 103
... The Fast Forcing feature is enabled on the corresponding interrupt. 11052C–ATARM–21-Nov- PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9G15 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS – 103 ...
Page 104
... Spurious Interrupt Vector Register” on page 99 • “AIC Debug Control Register” on page 100 • WPKEY: Write Protect KEY Should be written at value 0x414943 ("AIC" in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAM9G15 104 WPKEY ...
Page 105
... WPVSRC. • WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. Note: Reading AIC_WPSR automatically clears all fields. SAM9G15 105 — ...
Page 106
... SAM9G15 106 11052C–ATARM–21-Nov-11 ...
Page 107
... Status of the Last Reset – Either General Reset, Wake-up Reset, Software Reset, User Reset, Watchdog • External Reset Signal Shaping • AMBA – Interfaces to the ARM 11052C–ATARM–21-Nov-11 Reset ™ -compliant Interface ® Advanced Peripheral Bus SAM9G15 107 ...
Page 108
... Crystal Oscil- lator Characteristics in the Electrical Characteristics section of the product documentation. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Con- troller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on. SAM9G15 108 Reset Controller POR ...
Page 109
... The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. 11052C–ATARM–21-Nov-11 Figure 14-2 shows the block diagram of the NRST Manager. RSTC_SR URSTS NRSTL NRST RSTC_MR nrst_out External Reset Timer Slow Clock cycles. This gives the approximate duration of an assertion between 60 μs SAM9G15 user_reset ERSTL exter_nreset 109 ...
Page 110
... Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 14-4 SAM9G15 110 XXX BMS sampling delay = 3 cycles shows how the General Reset affects the reset signals ...
Page 111
... When the Main Supply is detected falling, the reset signals are immediately asserted. This tran- sition is synchronous with the output of the Main Supply POR. 11052C–ATARM–21-Nov-11 Startup Time Processor Startup XXX EXTERNAL RESET LENGTH BMS Sampling = 2 cycles SAM9G15 Any Freq. 0x0 = General Reset XXX 111 ...
Page 112
... EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How- ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. SAM9G15 112 Resynch. Processor Startup 2 cycles XXX ...
Page 113
... If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. 11052C–ATARM–21-Nov-11 Resynch. 2 cycles XXX >= EXTERNAL RESET LENGTH SAM9G15 Processor Startup 0x4 = User Reset 113 ...
Page 114
... WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. SAM9G15 114 Resynch. Processor Startup ...
Page 115
... When in Watchdog Reset: – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. 11052C–ATARM–21-Nov-11 Any Freq. Processor Startup = 3 cycles Any XXX proc_nreset signal. SAM9G15 0x2 = Watchdog Reset EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 115 ...
Page 116
... This transition is also detected on the Master Clock (MCK) rising edge (see 14-9). . Reading the RSTC_SR status register resets the URSTS bit . Figure 14-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) SAM9G15 116 read RSTC_SR 2 cycle resynchronization 11052C–ATARM–21-Nov-11 Figure ...
Page 117
... Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. 11052C–ATARM–21-Nov-11 Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write SAM9G15 Reset Back-up Reset - 0x0000_0001 0x0000_0000 - 0x0000_0000 117 ...
Page 118
... No effect KEY is correct, resets the peripherals. • EXTRST: External Reset effect KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM9G15 118 KEY 21 ...
Page 119
... Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress software command is being performed by the reset controller. The reset controller is ready for a software command software reset command is being performed by the reset controller. The reset controller is busy. SAM9G15 119 – ...
Page 120
... This field defines the external reset length. The external reset is asserted during a time of 2 allows assertion duration to be programmed between 60 μs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM9G15 120 29 28 ...
Page 121
... Programmable Periodic Interrupt • Time, Date and Alarm 32-bit Parallel Load 15.3 Block Diagram Figure 15-1. RTC Block Diagram Slow Clock: SLCK Bus Interface 11052C–ATARM–21-Nov-11 32768 Divider Time Bus Interface Entry Control SAM9G15 Date Interrupt RTC Interrupt Control 121 ...
Page 122
... The RTC has five programmable fields: month, date, hours, minutes and seconds. Each of these fields can be enabled or disabled to match the alarm condition: • If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled given month, date, hour/minute/second. SAM9G15 122 11052C–ATARM–21-Nov-11 ...
Page 123
... If the 12-hour mode is selected by means of the RTC_MODE register, a 12-hour value can be pro- grammed and the returned value on RTC_TIME will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIME register) to determine the range to be checked. SAM9G15 123 ...
Page 124
... Figure 15-2. Update Sequence SAM9G15 124 Begin Prepare TIme or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR No ACKUPD = 1 ? Yes Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR End Polling or IRQ (if enabled) 11052C–ATARM–21-Nov-11 ...
Page 125
... RTC_TIMR Read-write RTC_CALR Read-write RTC_TIMALR Read-write RTC_CALALR Read-write RTC_SR Read-only RTC_SCCR Write-only RTC_IER Write-only RTC_IDR Write-only RTC_IMR Read-only RTC_VER Read-only – – – – SAM9G15 Reset 0x0 0x0 0x0 0x01210720 0x0 0x01010000 0x0 – – – 0x0 0x0 – – 125 ...
Page 126
... The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL Value Name Description 0 WEEK Week change (every Monday at time 00:00:00) 1 MONTH Month change (every 01 of each month at time 00:00:00) 2 YEAR Year change (every January 1 at time 00:00:00) 3 – SAM9G15 126 – – – – – – 13 ...
Page 127
... All non-significant bits read zero. 11052C–ATARM–21-Nov- – – – – – – – – – – – – SAM9G15 – – – – – – – – – – – HRMOD 127 ...
Page 128
... HOUR: Current Hour The range that can be set (BCD) in 12-hour mode (BCD) in 24-hour mode. • AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode AM PM. All non-significant bits read zero. SAM9G15 128 – – ...
Page 129
... The range that can be set (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. 11052C–ATARM–21-Nov- YEAR CENT SAM9G15 26 25 DATE 18 17 MONTH 129 ...
Page 130
... This field is the alarm field corresponding to the BCD-coded hour counter. • AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled The hour-matching alarm is enabled. SAM9G15 130 – – ...
Page 131
... DATEEN: Date Alarm Enable 0 = The date-matching alarm is disabled The date-matching alarm is enabled. 11052C–ATARM–21-Nov- – – – – – – – SAM9G15 26 25 DATE 18 17 MONTH 10 9 – – – – – 0 – 131 ...
Page 132
... No calendar event has occurred since the last clear least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. SAM9G15 132 – ...
Page 133
... Clears corresponding status flag in the Status Register (RTC_SR). 11052C–ATARM–21-Nov- – – – – – – – – – – CALCLR TIMCLR SAM9G15 26 25 – – – – – – SECCLR ALRCLR ACKCLR 24 – 16 – 8 – 0 133 ...
Page 134
... No effect The second periodic interrupt is enabled. • TIMEN: Time Event Interrupt Enable effect The selected time event interrupt is enabled. • CALEN: Calendar Event Interrupt Enable effect. • The selected calendar event interrupt is enabled. SAM9G15 134 – – – ...
Page 135
... The selected calendar event interrupt is disabled. 11052C–ATARM–21-Nov- – – – – – – – – – – CALDIS TIMDIS SAM9G15 – – – – – – SECDIS ALRDIS ACKDIS – – 8 – 0 135 ...
Page 136
... TIM: Time Event Interrupt Mask 0 = The selected time event interrupt is disabled The selected time event interrupt is enabled. • CAL: Calendar Event Interrupt Mask 0 = The selected calendar event interrupt is disabled The selected calendar event interrupt is enabled. SAM9G15 136 – – ...
Page 137
... RTC_CALALR has contained invalid data since it was last programmed. 11052C–ATARM–21-Nov- – – – – – – – – – – – NVCALALR SAM9G15 26 25 – – – – – – NVTIMALR NVCAL NVTIM 24 – 16 – 8 – 0 137 ...
Page 138
... SAM9G15 138 11052C–ATARM–21-Nov-11 ...
Page 139
... Interfaces to the ARM Advanced Peripheral Bus 16.3 Block Diagram Figure 16-1. Periodic Interval Timer 0 MCK 20-bit Counter MCK/16 CPIV Prescaler CPIV 11052C–ATARM–21-Nov-11 PIT_MR PIV = 0 1 PIT_PIVR PIT_PIIR SAM9G15 set 0 PIT_SR PITS reset 0 1 12-bit Adder read PIT_PIVR PICNT PICNT PIT_MR PITIEN pit_irq 139 ...
Page 140
... PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. SAM9G15 140 Figure 16-2 illustrates 11052C– ...
Page 141
... Figure 16-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 11052C–ATARM–21-Nov-11 MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler 0 0 SAM9G15 1 141 ...
Page 142
... Periodic Interval Timer (PIT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register SAM9G15 142 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only Reset 0x000F_FFFF ...
Page 143
... PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt The bit PITS in PIT_SR asserts interrupt. 11052C–ATARM–21-Nov- – – – – – PIV PIV SAM9G15 – PITIEN PITEN PIV 143 ...
Page 144
... The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 11052C–ATARM–21-Nov- – – – – – – – – – – – – SAM9G15 – – – – – – – – – – – PITS 144 ...
Page 145
... Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 11052C–ATARM–21-Nov- PICNT CPIV CPIV SAM9G15 CPIV 145 ...
Page 146
... PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. SAM9G15 146 PICNT ...
Page 147
... Windowed, prevents the processor dead lock on the watchdog access • Counter May Be Stopped While the Processor is in Debug State or in Idle Mode • AMBA-compliant Interface – Interfaces to the ARM Advanced Peripheral Bus 11052C–ATARM–21-Nov-11 SAM9G15 147 ...
Page 148
... Block Diagram Figure 17-1. Watchdog Timer Block Diagram write WDT_MR WDT_CR WDRSTT WDT_MR WDD read WDT_SR or reset SAM9G15 148 WDT_MR WDV reload 1 0 12-bit Down Counter Current Value <= WDD = 0 set WDUNF reset set WDERR reset reload SLCK 1/128 WDT_MR WDRSTEN wdt_fault (to Reset Controller) ...
Page 149
... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. SAM9G15 149 11052C–ATARM–21-Nov-11 ...
Page 150
... Figure 17-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault SAM9G15 150 Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN is 0 11052C–ATARM–21-Nov-11 ...
Page 151
... Watchdog Timer (WDT) User Interface Table 17-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register SAM9G15 151 Name Access WDT_CR Write-only WDT_MR Read-write Once WDT_SR Read-only Reset - 0x3FFF_2FFF 0x0000_0000 11052C–ATARM–21-Nov-11 ...
Page 152
... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM9G15 152 KEY – – – – ...
Page 153
... The Watchdog runs when the processor is in debug state. 1: The Watchdog stops when the processor is in debug state. • WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable SAM9G15 153 WDDBGHLT ...
Page 154
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. SAM9G15 154 – ...
Page 155
... RTTWKEN RTT Alarm RTCWKEN RTC Alarm 11052C–ATARM–21-Nov-11 read SHDW_SR reset WAKEUP0 SHDW_SR set read SHDW_SR reset SHDW_MR RTTWK SHDW_SR set read SHDW_SR reset SHDW_MR RTCWK SHDW_SR set SAM9G15 SLCK Wake-up SHDN Shutdown Output Controller SHDW_CR Shutdown SHDW 155 ...
Page 156
... The software is able to control the pin (SHDW_CR) with the bit SHDW at 1. The shutdown is taken into account only 2 slow clock cycles after the write of SHDW_CR. This register is password-protected and so the value written SAM9G15 156 read SHDW_SR reset ...
Page 157
... RTC alarm status flag is cleared before shutting down the system.Otherwise, no rising edge of the status flag may be detected and the wake-up fails fail. 11052C–ATARM–21-Nov-11 pin is released new input change is detected before the counter reaches the corre- SAM9G15 157 ...
Page 158
... Shutdown Controller (SHDWC) User Interface Table 18-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register SAM9G15 158 Name Access SHDW_CR Write-only SHDW_MR Read-write SHDW_SR Read-only Reset - 0x0000_0003 0x0000_0000 11052C–ATARM–21-Nov-11 ...
Page 159
... Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 11052C–ATARM–21-Nov- KEY – – – – – – – – – pin. SAM9G15 – – – – – – – – SHDW 159 ...
Page 160
... Because of the internal synchronization of WKUP0, the (CPTWK Slow Clock cycles after the event on WKUP. • RTCWKEN: Real-time Clock Wake-up Enable 0 = The RTC Alarm signal has no effect on the Shutdown Controller The RTC Alarm signal forces the de-assertion of the SAM9G15 160 – ...
Page 161
... At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. • RTCWK: Real-time Clock Wake- wake-up alarm from the RTC occurred since the last read of SHDW_SR least one wake-up alarm from the RTC occurred since the last read of SHDW_SR. SAM9G15 161 – ...
Page 162
... SAM9G15 162 11052C–ATARM–21-Nov-11 ...
Page 163
... Four 32-bit General Purpose Backup Registers 19.3 General Purpose Backup Registers (GPBR) User Interface Table 19-1. Register Mapping Offset Register 0x0 General Purpose Backup Register 0 ... ... 0xc General Purpose Backup Register 3 11052C–ATARM–21-Nov-11 Name SYS_GPBR0 ... SYS_GPBR3 SAM9G15 Access Reset Read-write – ... ... Read-write – 163 ...
Page 164
... General Purpose Backup Register x Name: SYS_GPBRx Address: 0xFFFFFE60 [0], 0xFFFFFE64 [1], 0xFFFFFE68 [2], 0xFFFFFE6C [3] Access: Read-write • GPBR_VALUEx: Value of GPBR x 11052C–ATARM–21-Nov- GPBR_VALUEx GPBR_VALUEx GPBR_VALUEx GPBR_VALUEx SAM9G15 164 ...
Page 165
... Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through the Power Management Controller. • Enable the 32,768 Hz oscillator by setting the bit OSC32EN to 1. 11052C–ATARM–21-Nov-11 On Chip RC OSC Slow Clock XIN32 Oscillator XOUT32 SAM9G15 RCEN Slow Clock SLCK OSCSEL OSC32EN OSC32BYP 165 ...
Page 166
... Wait internal 32 kHz RC Startup Time for clock stabilization (software loop). • Switch from 32,768 Hz oscillator to internal RC by setting the bit OSCSEL to 0. • Wait 5 slow clock cycles for internal resynchronization. • Disable the 32,768 Hz oscillator by setting the bit OSC32EN to 0. SAM9G15 166 11052C–ATARM–21-Nov-11 ...
Page 167
... Slow Clock Configuration (SCKC) User Interface Table 20-1. Register Mapping Offset Register 0x0 Slow Clock Configuration Register 11052C–ATARM–21-Nov-11 Name Access SCKC_CR Read-write SAM9G15 Reset 0x0000_0001 167 ...
Page 168
... Slow clock is 32,768 Hz oscillator. 11052C–ATARM–21-Nov- – – – – – – – – – – – OSCSEL SAM9G15 26 25 – – – – – – OSC32BYP OSC32EN RCEN 24 – 16 – 8 – 0 168 ...
Page 169
... MHz Fast RC Oscillator • PLLACK is the output of the Divider and 400 to 800 MHz programmable PLL (PLLA) • UPLLCK is the output of the 480 MHz UTMI PLL (UPLL) 11052C–ATARM–21-Nov-11 Section 22.13 ”Power Management Controller (PMC) User SAM9G15 Interface”. However, 169 ...
Page 170
... OSC32BYP to accept an external slow clock on XIN32. The internal 32 kHz RC oscillator and the 32,768 Hz oscillator can be enabled by setting to 1, respectively, RCEN bit and OSC32EN bit in the System Controller user interface. The OSCSEL command selects the slow clock source. SAM9G15 170 Clock Generator On Chip ...
Page 171
... Enable the bypass path OSC32BYP bit set to 1. • Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0. 11052C–ATARM–21-Nov-11 Clock Generator On Chip RC OSC Slow Clock XIN32 Oscillator XOUT32 SAM9G15 RCEN Slow Clock SLCK OSCSEL OSC32EN OSC32BYP 171 ...
Page 172
... Switch from 32768 Hz oscillator to internal RC by setting the bit OSCSEL to 0. • Wait 5 slow clock cycles for internal resynchronization. • Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0. • Switch the master clock back to the slow clock domain SAM9G15 172 11052C–ATARM–21-Nov-11 ...
Page 173
... Slow clock is 32768 Hz oscillator 11052C–ATARM–21-Nov- – – – – – – – – – – – OSCSEL SAM9G15 26 25 – – – – – – OSC32BYP OSC32EN RCEN 24 – 16 – 8 – 0 173 ...
Page 174
... The main clock can be generated either by an external 12 MHz crystal oscillator or by the on- chip 12 MHz RC oscillator. This fast RC oscillator allows the processor to start or restart in a few microseconds when 12 MHz internal RC is selected. The 12 MHz crystal oscillator can be bypassed by setting the bit MOSCXTBY to accept an exter- nal main clock on XIN. SAM9G15 174 MOSCRCEN MOSCRCF 12 MHz ...
Page 175
... Crystal Startup Time Wait MOSCRCS = 1 System switches on Main Clock to speed-up the boot System is running at 12 MHz External oscillator is started for better accuracy MOSCXTEN = 1 MOSCSEL = 0 SAM9G15 MOSCRCEN Main Clock MOSCSEL MOSCXTEN MOSCXTBY Wait MOSCXTS = 1 User switches on external oscillator MOSCSEL=1 Wait while MOSCSELS =1 ...
Page 176
... Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) can trigger an interrupt to the processor. 21.6 MHz Crystal Oscillator After reset, the MHz Crystal Oscillator is disabled and it is not selected as the source of MAINCK. SAM9G15 176 11052C–ATARM–21-Nov-11 ...
Page 177
... Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main Clock Frequency Register (CKGR_MCFR) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 11052C–ATARM–21-Nov-11 SAM9G15 177 ...
Page 178
... MAINCK, the 12 MHz frequency must also be selected because the UTMI PLL multiplier contains a built-in multiplier obtain the USB High Speed 480 MHz MHz crystal is needed to use the USB. SAM9G15 178 shows the block diagram of the divider and PLLA block. DIVA ...
Page 179
... The user has to load the number of Slow Clock cycles required to cover the UTMI PLL transient time into the PLLCOUNT field. 11052C–ATARM–21-Nov-11 UPLLEN MAINCK UTMI PLL UPLLCOUNT UTMI PLL SLCK Counter SAM9G15 UPLLCK LOCKU 179 ...
Page 180
... Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery SAM9G15 180 DDR clock is not available when Master Clock (MCK) equals Processor Clock (PCK). ...
Page 181
... This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. Figure 22-1. Master Clock Controller MAINCK PLLACK UPLLCK 11052C–ATARM–21-Nov-11 PMC_MCKR PMC_MCKR CSS SLCK Master Clock Prescaler PRES MCK To the Processor Clock Controller (PCK) SAM9G15 181 ...
Page 182
... Note: The ARM Wait for Interrupt mode is entered by means of CP15 coprocessor operation. Refer to the Atmel application note, Systems, lit. number 6217. When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. SAM9G15 182 USBS USBDIV /1.5 /2 ...
Page 183
... To write the division factor on a particular peripheral, the user needs to write a WRITE command, the peripheral ID and the chosen divi- sion factor. To read the current division factor on a particular peripheral, the user just needs to write the READ command and the peripheral ID. 11052C–ATARM–21-Nov-11 SAM9G15 183 ...
Page 184
... Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register to be set. This can be done either by polling the status register or by wait- ing the interrupt line to be raised if the associated interrupt to MOSCS has been enabled in the PMC_IER register. 2. Setting PLLA and divider: SAM9G15 184 11052C–ATARM–21-Nov-11 ...
Page 185
... The CSS field is used to select the clock source of the Master Clock and Processor Clock dividers. By default, the selected clock source is slow clock. The PRES field is used to control the Master/Processor Clock prescaler. The user can choose between different values ( 16, 32, 64). Prescaler output is the selected 11052C–ATARM–21-Nov-11 write_register(CKGR_PLLAR,0x00040805) SAM9G15 185 ...
Page 186
... The Master Clock is main clock divided by 16. SAM9G15 186 IF PLLA clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLAR, the MCKRDY flag will go low while PLLA is unlocked. Once PLLA is locked again, LOCK goes high and MCKRDY is set ...
Page 187
... Depending on the system used, 19 peripheral clocks can be enabled or disabled. The PMC_PCR provides a clear view as to which peripheral clock is enabled. Note: Code Examples: write_register(PMC_PCER,0x00000110) Peripheral clocks 4 and 8 are enabled. write_register(PMC_PCDR,0x00000010) Peripheral clock 4 is disabled. 11052C–ATARM–21-Nov-11 Each enabled peripheral clock corresponds to Master Clock. SAM9G15 187 ...
Page 188
... Table 22-1. To Main Clock SLCK PLL Clock Notes: Table 22-2. To PLLA Clock UPLL Clock SAM9G15 188 and Table 22-2 give the worst case timings required for the Master Clock to switch Clock Switching Timings (Worst Case) From Main Clock – 0.5 x Main Clock + 4.5 x SLCK ...
Page 189
... Figure 22-3. Switch Master Clock from Slow Clock to PLL Clock Write PMC_MCKR Figure 22-4. Switch Master Clock from Main Clock to Slow Clock Write PMC_MCKR 11052C–ATARM–21-Nov-11 Slow Clock PLL Clock LOCK MCKRDY Master Clock Slow Clock Main Clock MCKRDY Master Clock SAM9G15 189 ...
Page 190
... Figure 22-5. Change PLLA Programming Write CKGR_PLLAR Figure 22-6. Programmable Clock Output Programming Write PMC_PCKx Write PMC_SCER Write PMC_SCDR SAM9G15 190 Slow Clock PLLA Clock LOCKA MCKRDY Master Clock PLL Clock PCKRDY PCKx Output PLL Clock is selected Slow Clock PCKx is enabled PCKx is disabled ...
Page 191
... PMC_IER Write-only PMC_IDR Write-only PMC_SR Read-only PMC_IMR Read-only – – PMC_PLLICPR Write-only – – PMC_WPMR Read-write PMC_WPSR Read-only – – PMC_PCR Read-write SAM9G15 Reset N.A. N.A. 0x0000_0005 N.A. – 0x0000_0000 – 0x1020_0000 0x0100_0008 0x0000_0000 0x0000_3F00 – 0x0000_0001 – 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 – N.A. N.A. ...
Page 192
... No effect Enables the UHP48M and UHP12M OHCI clocks. • UDP: USB Device Clock Enable effect Enables the USB Device clock. • PCKx: Programmable Clock x Output Enable effect Enables the corresponding Programmable Clock output. SAM9G15 192 – – – ...
Page 193
... Disables the corresponding Programmable Clock output. 11052C–ATARM–21-Nov- – – – – – – – – – – SMDCK LCDCK SAM9G15 – – – – – PCK1 PCK0 2 1 DDRCK – PCK – – 193 ...
Page 194
... The UHP48M and UHP12M OHCI clocks are enabled. • UDP: USB Device Port Clock Status 0 = The USB Device clock is disabled The USB Device clock is enabled. • PCKx: Programmable Clock x Output Status 0 = The corresponding Programmable Clock output is disabled The corresponding Programmable Clock output is enabled. SAM9G15 194 – – ...
Page 195
... Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC. 11052C–ATARM–21-Nov- PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9G15 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 - - 195 ...
Page 196
... PID15 PID14 7 6 PID7 PID6 • PIDx: Peripheral Clock x Disable effect Disables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. SAM9G15 196 PID29 PID28 PID27 PID21 PID20 ...
Page 197
... PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. 11052C–ATARM–21-Nov- PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9G15 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 – – 197 ...
Page 198
... Specifies the number of Slow Clock cycles multiplied by 8 for the UTMI PLL start-up time. • BIASEN: UTMI BIAS Enable 0 = The UTMI BIAS is disabled The UTMI BIAS is enabled. • BIASCOUNT: UTMI BIAS Start-up Time Specifies the number of Slow Clock cycles for the UTMI BIAS start-up time. SAM9G15 198 – ...
Page 199
... The Main Crystal Oscillator is selected. • CFDEN: Clock Failure Detector Enable 0 = The Clock Failure Detector is disabled. 11052C–ATARM–21-Nov- – – – KEY MOSCXTST – – MOSCRCEN SAM9G15 – CFDEN MOSCSEL – MOSCXTBY MOSCXTEN 199 ...
Page 200
... MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINFRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled The Main Oscillator has been enabled previously and MAINF value is available. SAM9G15 200 – ...