SAM9G35 Atmel Corporation, SAM9G35 Datasheet
SAM9G35
Specifications of SAM9G35
Related parts for SAM9G35
SAM9G35 Summary of contents
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... Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input – Individually Programmable Open-drain, Pull-up and pull-down resistor, Synchronous Output • Package – 217-ball BGA, pitch 0.8 mm ® Processor running 400 MHz @ 1.0V +/- 10% AT91SAM ARM-based Embedded MPU SAM9G35 11053B–ATARM–22-Sep-11 ...
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... Description The SAM9G35 is a member of the Atmel series of 400 MHz ARM926 embedded MPUs that sup- port high bandwidth communication and advanced user interfaces and are optimized for industrial applications such as building automation, data loggers, POS terminals, alarm systems and medical equipment. ...
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... Block Diagram Figure 2-1. SAM9G35 Block Diagram 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 PIO PIO SAM9G35 SAM9G35 3 3 ...
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... Fast Interrupt Input PA0-PA31 Parallel IO Controller A PB0-PB18 Parallel IO Controller B PC0-PC31 Parallel IO Controller C PD0-PD21 Parallel IO Controller D SAM9G35 SAM9G35 4 4 gives details on the signal names classified by peripheral. Clocks, Oscillators and PLLs Shutdown, Wakeup Logic ICE and JTAG Reset/Test Debug Unit - DBGU Advanced Interrupt Controller - AIC ...
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... Multimedia Card 1 Slot A Data 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 External Bus Interface - EBI Static Memory Controller - SMC NAND Flash Support DDR2/SDRAM/LPDDR Controller High Speed MultiMedia Card Interface - HSMCI0-1 SAM9G35 SAM9G35 Type Active Level I/O I/O Output Input Low Output Low ...
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... SPIx_NPCS0 SPI Peripheral Chip Select 0 SPIx_NPCS1-SPIx_NPCS3 SPI Peripheral Chip Select TWDx Two-wire Serial Data TWCKx Two-wire Serial Clock SAM9G35 SAM9G35 6 6 Universal Asynchronous Receiver Transmitter - UARTx Synchronous Serial Controller - SSC Timer/Counter - TCx x=0..5 Serial Peripheral Interface - SPIx Two-Wire Interface -TWIx Type Active Level ...
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... Pulse Width Modulation Controller- PWMC USB Host High Speed Port - UHPHS USB Device High Speed Port - UDPHS RMII Ethernet 10/100 - EMAC LCD Controller - LCDC Analog-to-Digital Converter - ADC SAM9G35 SAM9G35 Type Active Level Output Analog Analog Analog Analog ...
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... Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference DIBN Soft Modem Signal DIBP Soft Modem Signal 4. Package and Pinout The SAM9G35 is available in 217-ball BGA package. 4.1 Overview of the 217-ball BGA Package Figure 4-1 Figure 4-1. SAM9G35 SAM9G35 8 8 Soft Modem - SMD shows the orientation of the 217-ball BGA Package. ...
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... SAM9G35 I/O Type Description Voltage Range Analog 1.65-3.6V 1.65-3.6V 1.65-3.6V 3.0-3.6V I 1.65-1.95V, 3.0- 3.6V 1.65-1.95V, 3.0- 3.6V 1.65-1.95V, 3.0- 3.6V 3.0-3.6V 1.65-3.6V 0.9-1.1V I 3.0-3.6V I/O 3.0-3.6V I/O 1.65-3.6V I/O 3.0-3.6V I/O SAM9G35 I/O Type Assignment and Frequency I/O Frequency Charge Load Output (MHz) (pF) Current 16mA 40mA (peak) 50 (3.3V) 133 30 (1.8V) 50 (3.3V (1.8V) 133 0.25 10 ...
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... Indicates whether the signal is input or output state. • “PU”/”PD” Indicates whether Pull-Up, Pull-Down or nothing is enabled. • “ST” Indicates if Schmitt Trigger is enabled. Note: SAM9G35 SAM9G35 10 10 SAM9G35 I/O Type Assignment and Frequency (Continued) I/O Frequency Charge Load (MHz) (pF 480 10 50 ...
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... SCK0 I/O TXD1 I/O RXD1 I/O TXD2 I/O RXD2 I/O DRXD I/O DTXD I/O SPI0_MISO I/O SPI0_MOSI I/O SPI0_SPCK SPI0_NPCS I/O 0 I/O MCI0_DA0 I/O MCI0_CDA I/O MCI0_CK I/O MCI0_DA1 I/O MCI0_DA2 I/O MCI0_DA3 SAM9G35 SAM9G35 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal O SPI1_NPCS1 O I SPI0_NPCS2 O O MCI1_DA1 I/O ETX0 I MCI1_DA2 I/O ETX1 I/O MCI1_DA3 I SPI0_NPCS1 O I SPI1_NPCS0 I I/O MCI1_DA0 ...
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... GPIO_CLK PB4 D1 VDDANA GPIO PB5 E3 VDDANA GPIO_ANA PB6 B3 VDDANA GPIO_ANA PB7 C2 VDDANA GPIO_ANA PB8 C5 VDDANA GPIO_ANA PB9 C1 VDDANA GPIO_ANA PB10 B2 VDDANA GPIO_ANA PB11 A3 SAM9G35 SAM9G35 12 12 Alternate PIO Peripheral A Dir Signal Dir Signal Dir I/O TIOA0 I/O I/O TIOA1 I/O I/O TIOA2 I/O I/O TCLK0 I I/O TCLK1 I I/O TCLK2 I I/O TIOB0 I/O I/O ...
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... I/O LCDDAT0 I/O LCDDAT1 I/O LCDDAT2 I/O LCDDAT3 I/O LCDDAT4 I/O LCDDAT5 I/O LCDDAT6 I/O LCDDAT7 I/O LCDDAT8 I/O LCDDAT9 I/O LCDDAT10 I/O LCDDAT11 I/O LCDDAT12 I/O LCDDAT13 I/O LCDDAT14 I/O LCDDAT15 SAM9G35 SAM9G35 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal PWM1 O PWM2 O PWM3 ADTRG I O TWD1 O TWCK1 O TIOA3 O TIOB3 O TCLK3 O TIOA4 O TIOB4 O TCLK4 ...
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... P15 P12 VDDNF EBI PD4 P14 VDDNF EBI PD5 N14 VDDNF EBI PD6 R15 VDDNF EBI PD7 M14 VDDNF EBI PD8 N16 VDDNF EBI PD9 SAM9G35 SAM9G35 14 14 Alternate PIO Peripheral A Dir Signal Dir Signal Dir I/O LCDDAT16 O I/O LCDDAT17 O I/O LCDDAT18 O I/O LCDDAT19 O I/O LCDDAT20 O I/O ...
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... D25 I/O D26 I/O D27 I/O D28 I/O D29 I/O D30 I/O D31 SAM9G35 SAM9G35 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal A20 O O A23 O O A24 O O A25 O O NCS2 O O NCS4 O O NCS5 ...
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... D17 VDDIOM EBI_O A12 C17 VDDIOM EBI_O A13 E16 VDDIOM EBI_O A14 D16 VDDIOM EBI_O A15 C16 VDDIOM EBI_O A16 B17 VDDIOM EBI_O A17 E15 VDDIOM EBI_O A18 SAM9G35 SAM9G35 16 16 Alternate PIO Peripheral A Dir Signal Dir Signal Dir I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O NBS0 ...
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... O I/O I I/O DFSDP I/O I/O DFSDM I/O I/O DHSDP I/O I/O DHSDM I/O I/O I/O I/O I/O I/O I/O I/O I SAM9G35 SAM9G35 PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal Reset State Signal, Dir, Dir PU, PD ...
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... CLOCK XIN32 A5 VDDBU CLOCK XOUT32 T12 VDDOSC CLOCK XIN U12 VDDOSC CLOCK XOUT 5. Power Considerations 5.1 Power Supplies The SAM9G35 has several types of power supply pins. Table 5-1. SAM9G35 Power Supplies Name Voltage Range, nominal VDDCORE 0.9-1.1V, 1.0V 1.65-1.95V, 1.8V VDDIOM 3.0-3.6V, 3.3V 1.65-1.95V, 1.8V VDDNF 3.0-3.6V, 3.3V VDDIOP0 1.65-3.6V VDDIOP1 1.65-3.6V VDDBU 1 ...
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... Memories Figure 6-1. SAM9G35 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1 DDR2/LPDDR SDR/LPSDR 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 0x4000 0000 EBI Chip Select 3 ...
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... Embedded Memories 6.2.1 Internal SRAM The SAM9G35 embeds a total of 32 Kbytes of high-speed SRAM. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. After Remap, the SRAM also becomes available at address 0x0. 6.2.2 Internal ROM The SAM9G35 embeds an Internal ROM, which contains the SAM-BA program ...
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... CAS Latency Supported • Auto Precharge Command Not Used • SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported – Clock Frequency Change in Precharge Power-down Mode Not Supported 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 Average Latency of Transactions) SAM9G35 SAM9G35 21 21 ...
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... System Controller can be addressed from a single pointer by using the stan- dard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KBytes. Figure 7-1 on page 23 Figure 6-1 on page 19 peripherals. SAM9G35 SAM9G35 22 22 shows the System Controller block diagram. shows the mapping of the User Interface of the System Controller 11053B–ATARM–22-Sep-11 ...
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... Figure 7-1. SAM9G35 System Controller Block Diagram periph_irq[2..30] pit_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP XIN32 SLOW CLOCK XOUT32 OSC XIN 12MHz MAIN OSC XOUT UPLL PLLA periph_nreset periph_nreset periph_clk[2..3] PA0-PA31 PB0-PB18 ...
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... Chip ID: 0x819A_05A1 • Chip ID Extension: 1 • JTAG ID: 0x05B2_F03F • ARM926 TAP ID: 0x0792_603F 7.2 Backup Section The SAM9G35 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • Real Time Counter (RTC) • Shutdown Controller • 4 Backup Registers • Slow Clock Control Register (SCKCR) • ...
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... SAM9G35 SAM9G35 25 25 Figure 6-1, the Peripherals are mapped in the upper 256 Mbytes of the address defines the Peripheral Identifiers of the SAM9G35. A peripheral identifier is required Peripheral Identifiers Instance Name Instance Description AIC Advanced Interrupt Controller System Controller Interrupt SYS PIOA,PIOB Parallel I/O Controller A and B ...
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... Peripheral Signal Multiplexing on I/O Lines The SAM9G35 features 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls 32 lines, 19 lines, 32 lines and 22 lines respectively for PIOA, PIOB, PIOC and PIOD. Each line can be assigned to one of three peripheral functions ...
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... SAM9G35 SAM9G35 27 27 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
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... SAM9G35 SAM9G35 28 28 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
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... Based on ARM Architecture v5TEJ with Jazelle Technology ® High-performance 32-bit Instruction Set ® High Code Density 16-bit Instruction Set ® 8-bit Instruction Set SAM9G35 SAM9G35 ™ family of general-purpose microproces ...
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... Separate AMBA AHB Buses for Both the 32-bit Data Interface and the 32-bit • Bus Interface Unit – Arbitrates and Schedules AHB Requests – Enables Multi-layer AHB to be Implemented – Increases Overall Bus Bandwidth – Makes System Architecture Mode Flexible SAM9G35 SAM9G35 30 30 Instructions Interface 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
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... Interface ARM9EJ-S Processor Core Read Data Data Instruction Address MMU Instruction Data TLB TLB Data Address AHB Interface and Write Buffer AMBA AHB SAM9G35 SAM9G35 ETM9 Trace Port Interface Instruction Fetches Address ITCM Interface Instruction TCM Instruction Address Instruction Cache 31 31 ...
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... ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. SAM9G35 SAM9G35 32 32 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
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... R10 R10 R11 R11 Interrupt Mode Fast Interrupt Mode R10 R10 R11 R11 SAM9G35 SAM9G35 R8_FIQ R9_FIQ R10_FIQ R11_FIQ 33 33 ...
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... The Thumb state register set is a subset of the ARM state set. The programmer has direct access to: • Eight general-purpose registers r0-r7 • Stack pointer, SP • Link register, LR (ARM r14) • PC • CPSR SAM9G35 SAM9G35 34 34 Abort Mode Undefined Mode R12 R12 R13_ABORT ...
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... Reserved Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than shows the status register format, where: SAM9G35 SAM9G35 0 Mode Mode bits Thumb state bit FIQ disable IRQ disable 35 35 ...
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... Execute stage in the pipeline. If the instruction is not executed, for example because a branch occurs while the pipeline, the abort does not take place. SAM9G35 SAM9G35 36 36 into LR (current PC(r15 depending on the exception). ...
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... Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte SAM9G35 SAM9G35 Mnemonic Operation MVN Move Not ADC Add with Carry SBC Subtract with Carry RSC Reverse Subtract with Carry ...
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... The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: • Branch instructions • Data processing instructions • Load and Store instructions SAM9G35 SAM9G35 38 38 ARM Instruction Mnemonic List (Continued) Operation Load Register Byte with ...
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... Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack Conditional Branch SAM9G35 SAM9G35 Mnemonic Operation MVN Move Not ADC Add with Carry SBC Subtract with Carry CMN Compare Negated NEG ...
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... Table 9-5. Register Notes: SAM9G35 SAM9G35 40 40 CP15 Registers Name ( Code (1) 0 Cache type (1) 0 TCM status 1 Control 2 Translation Table Base 3 Domain Access Control 4 Reserved (1) 5 Data fault Status (1) 5 Instruction fault status 6 Fault Address 7 Cache Operations 8 TLB operations (2) 9 cache lockdown ...
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... For more details, see Chapter 2 in ARM926EJ-S TRM. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2 SAM9G35 SAM9G35 CRn CRm ...
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... Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modi- SAM9G35 SAM9G35 42 42 Mapping Details Mapping Size Access Permission By ...
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... This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 SAM9G35 SAM9G35 43 43 ...
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... The Write Buffer can hold words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. SAM9G35 SAM9G35 44 44 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
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... Any ARM9EJ-S core request that is not words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 SAM9G35 SAM9G35 45 45 ...
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... The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. SAM9G35 SAM9G35 46 46 Single transfer of word, half word, or byte: • data write (NCNB, NCB, WT that has missed in DCache) • ...
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... Debug and Test 10.1 Description The SAM9G35 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as down- loading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communica- tion Channel ...
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... Block Diagram Figure 10-1. Debug and Test Block Diagram TAP: Test Access Port SAM9G35 SAM9G35 48 48 ICE/JTAG Boundary TAP Port ARM9EJ-S ICE-RT ARM926EJ-S DMA DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR Reset and TST Test DTXD DRXD 11053B–ATARM–22-Sep-11 ...
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... Figure 10-2. Application Debug and Trace Environment Example 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 shows a complete debug environment example. The ICE/JTAG interface is used for ICE/JTAG Interface ICE/JTAG Connector RS232 SAM9 Connector SAM9-based Application Board SAM9G35 SAM9G35 Host Debugger Terminal 49 49 ...
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... In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 10-3. Application Test Environment Example SAM9G35 SAM9G35 50 50 shows a test environment example. Test vectors are sent and interpreted by the tes- Test Adaptor ...
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... ICE and JTAG Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select Returned Test Clock JTAG Selection Debug Unit Debug Receive Data Debug Transmit Data SAM9G35 SAM9G35 Type Active Level Input/Output Low Input High Input Low Input Input Output ...
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... TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. SAM9G35 SAM9G35 52 52 ™ is supported via the ICE/JTAG port connected to a 11053B– ...
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... ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant not possible to switch directly between JTAG and ICE operations. A chip reset must be per- formed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 SAM9G35 SAM9G35 53 53 ...
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... VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B2F • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B2_F03F. SAM9G35 SAM9G35 PART NUMBER ...
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... XTal or external clock frequency detection • attempt to retrieve a valid code from external non-volatile memories (NVM) • execution of a monitor called SAM-BA Monitor, in case no valid application has been found on any NVM 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 (Section 11.1 “ROM Code”) SAM9G35 SAM9G35 55 55 ...
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... MHz external clock or crystal frequency running at 12 MHz is found, then the PLLA is configured to allow communication on the USB link for the SAM-BA Monitor; else the Main Clock is switched to the internal 12 MHz Fast RC, but USB will not be activated. SAM9G35 SAM9G35 56 56 Figure Chip Setup ...
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... BSCR Value. Boot Sequence Register Values NAND SPI0 NPCS0 SDCard Flash SAM9G35 SAM9G35 Figure 11-2 “NVM Bootloader SAM-BA SPI0 NPCS1 TWI EEPROM Monitor ...
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... SPI0 CS0 Flash Boot No SD Card Boot No NAND Flash Boot No SPI0 CS1 Flash Boot No TWI EEPROM Boot No SAM-BA Monitor SAM9G35 SAM9G35 Copy from SPI Flash to SRAM Y es Copy from SD Card to SRAM Y es Copy from NAND Flash to SRAM Y es Copy from ...
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... Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals. Perform the REMAP and set the jump to the downloaded application End SAM9G35 SAM9G35 Restore the reset values for the peripherals and Jump to next boot solution 59 59 ...
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... Figure 11-6. B Opcode Unconditional instruction: 0xE for bits Load PC with PC relative addressing instruction: – 0xF – I==0 (12-bit immediate value) – P==1 (pre-indexed) – U offset added (U==1) or subtracted (U==0) – W==1 SAM9G35 SAM9G35 60 60 0x0000_0000 Internal ROM 0x0010_0000 Internal ROM 0x0030_0000 Internal SRAM 28 27 ...
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... ONFI parameters for ONFI compliant memories. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 Size of the code to download in bytes ea000006 B 0x20 eafffffe B 0x04 ea00002f B _main eafffffe B 0x0c eafffffe B 0x10 <- Code size = 4660 bytes 00001234 B 0x14 eafffffe B 0x18 SAM9G35 SAM9G35 ...
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... Figure 11-8. Boot NAND Flash Download SAM9G35 SAM9G35 62 62 Start Initialize NAND Flash interface Send Reset command No First page contains valid header Yes Read NAND Flash and PMECC parameters Read NAND Flash and PMECC parameters from the header Copy the valid code from external NVM to internal SRAM ...
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... If the header is valid, the Boot Program will continue with the detection of valid code. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep- eccOffset SAM9G35 SAM9G35 26 25 eccOffset 18 17 sectorSize 10 9 spareSize 2 1 nbSectorPerPage usePmecc ...
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... PMECC base address, pPMERRLOC: pointer to the PMERRLOC base address, PMECC_desc: pointer to the PMECC descriptor, PMECC_status: the status returned by the read of PMECCISR register; SAM9G35 SAM9G35 64 64 Booting on 16-bit NAND Flash is not possible, only 8-bit NAND Flash memories are supported. AT91PS_PMERRLOC pPMERRLOC, ...
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... TT_MAX + 1]; /* polynom order */ short lmu[TT_MAX + 1]; SAM9G35 SAM9G35 65 65 ...
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... SPI DataFlash. It uses only one valid code detection: analysis of ARM exception vectors. The SPI Flash read is done by means of a Continuous Read command from address 0x0. This command is 0xE8 for DataFlash and 0x0B for Serial Flash devices. SAM9G35 SAM9G35 66 66 0x0010_0000 ROM Code ...
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... Mbits 4 Mbits 8 Mbits 16 Mbits 32 Mbits 64 Mbits 2 C-compatible TWI EEPROM memories using 7-bit device contains a list of pins that are driven during the boot program execution. These pins SAM9G35 SAM9G35 Page Size (bytes) Number of Pages 264 512 264 1024 264 2048 264 4096 ...
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... Check if USB Device enumeration has occurred – Check if characters have been received on the DBGU Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as listed in SAM9G35 SAM9G35 68 68 PIO Driven during Boot Program Execution Peripheral ...
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... Address,# write a word Address, Value# read a word Address,# send a file Address,# receive a file Address, NbOfBytes# go Address# display version No argument SAM9G35 SAM9G35 No No Character(s) received on DBGU ? Yes Run monitor Wait for command on the DBGU link Example N# T# O200001,CA# o200001,# H200002,CAFE# ...
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... CRC16 Figure 11-11 SAM9G35 SAM9G35 70 70 There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. ...
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... Windows 98SE to Windows XP Handled Standard Requests Definition Returns the current device configuration value. Sets the device address for all future device access. Sets the device configuration. Returns the current device configuration value. SAM9G35 SAM9G35 Device ® . The CDC document, available ...
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... BA Boot commands are sent by the host through endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. SAM9G35 SAM9G35 72 72 Handled Standard Requests (Continued) Definition Returns status for the specified recipient ...
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... Embedded Characteristics • VDDBU powered • Product-dependent order 12.3 Boot Sequence Controller Registers (BSC) User Interface Table 12-1. Register Mapping Offset Register 0x0 Boot Sequence Configuration Register 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 Name BSC_CR SAM9G35 SAM9G35 Access Reset Read-write – ...
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... Factory Value:0x0000_0000 • BOOTx: Boot media sequence Is defined in the product-dependent ROM code. • BOOTKEY 0xB5 (VALID): valid boot key To avoid spurious writing, this key is necessary for write accesses. SAM9G35 SAM9G35 BOOTKEY BOOT BOOT ...
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... Easy Debugging by Preventing Automatic Operations when Protect Models Are • Fast Forcing – Permits Redirecting any Normal Interrupt Source to the Fast Interrupt of the 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 External Interrupts External Sources Enabled Processor SAM9G35 SAM9G35 ® Processor 75 75 ...
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... General Interrupt Mask – Provides Processor Synchronization on Events Without Triggering an Interrupt • Write Protected Registers 13.3 Block Diagram Figure 13-1. Block Diagram 13.4 Application Block Diagram Figure 13-2. Description of the Application Block SAM9G35 SAM9G35 76 76 FIQ AIC IRQ0-IRQn Up to Thirty-two Sources Embedded PeripheralEE Embedded ...
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... PIOIRQ Internal Source Input Stage Embedded Peripherals I/O Line Description Pin Description Fast Interrupt Interrupt 0 - Interrupt n I/O Lines Signal AIC FIQ AIC IRQ SAM9G35 SAM9G35 ARM Processor Fast nFIQ Interrupt Controller nIRQ Interrupt Fast Processor Priority Forcing Clock Controller Power Management Controller User Interface ...
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... All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clear- ing or setting interrupt sources programmed in level-sensitive mode has no effect. SAM9G35 SAM9G35 78 78 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
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... Controller” on page AIC_SMRI (SRCTYPE) Level/ AIC_IPR Edge Edge Detector Set Clear 82.) The automatic clear reduces See “Fast Forcing” on “Priority Controller” on page AIC_IMR Fast Interrupt Controller or Priority Controller AIC_IECR FF AIC_IDCR SAM9G35 SAM9G35 79 79 ...
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... Figure 13-5. External Interrupt Source Input Stage High/Low Source i Detector Set AIC_ISCR AIC_ICCR 13.8.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including: • The time the software masks the interrupts. SAM9G35 SAM9G35 80 80 AIC_SMRi SRCTYPE Level/ AIC_IPR Edge Pos./Neg. Edge Clear AIC_IMR ...
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... IRQ or FIQ (Negative Edge) nIRQ Maximum IRQ Latency = 4 Cycles nFIQ Maximum FIQ Latency = 4 Cycles External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles SAM9G35 SAM9G35 81 81 ...
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... The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority interrupt condition happens (or is pending) during the interrupt treatment in SAM9G35 SAM9G35 82 82 Internal Interrupt Edge Triggered Source ...
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... This section gives an overview of the fast interrupt handling sequence when using the AIC assumed that the programmer understands the architecture of the ARM processor, and espe- cially the processor interrupt modes and the associated status bits assumed that: 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 PC,[PC,# -&F20] SAM9G35 SAM9G35 83 83 ...
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... PC. This has the effect of returning from the interrupt to whatever was being exe- cuted before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq. Note: SAM9G35 SAM9G35 84 84 priority. The current level is the priority level of the current interrupt. must be read in order to de-assert nIRQ. ...
Page 85
... The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automati- 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 PC,[PC,# -&F20] SAM9G35 SAM9G35 85 85 ...
Page 86
... Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). SAM9G35 SAM9G35 86 86 The “F” bit in SPSR is significant set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted ...
Page 87
... AIC_IPR Input Stage Automatic Clear AIC_IMR Read FVR if Fast Forcing is disabled on Sources 1 to 31. AIC_FFSR AIC_IPR Input Stage AIC_IMR Automatic Clear Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n. SAM9G35 SAM9G35 nFIQ Priority Manager nIRQ 87 87 ...
Page 88
... Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt strongly recommended to use this mask with caution. SAM9G35 SAM9G35 88 88 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
Page 89
... Spurious Interrupt Vector Register” on page 103 • “AIC Debug Control Register” on page 104 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 (AIC_WPSR) is set and the WPVSRC field indicates in which register SAM9G35 SAM9G35 AIC Write Protect Mode Register AIC Write 89 89 ...
Page 90
... The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. 2. PID2...PID31 bit fields refer to the identifiers as defined in the Peripheral Identifiers Section of the product datasheet. SAM9G35 SAM9G35 90 90 Register Source Mode Register 0 ...
Page 91
... Positive edge triggered for internal source Negative edge triggered for external source High level Sensitive for internal source High level Sensitive for external source Positive edge triggered for internal source Positive edge triggered for external source SAM9G35 SAM9G35 – – – ...
Page 92
... This register can only be written if the WPEN bit is cleared in • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source. SAM9G35 SAM9G35 VECTOR VECTOR 13 12 ...
Page 93
... The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep- IRQV IRQV IRQV IRQV SAM9G35 SAM9G35 ...
Page 94
... FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU. SAM9G35 SAM9G35 FIQV 21 20 ...
Page 95
... The Interrupt Status Register returns the current interrupt source number. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep- – – – – – – – – – – SAM9G35 SAM9G35 – – – – – – – – – IRQID 95 95 ...
Page 96
... Reset: 0x0 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Mask 0 = Corresponding interrupt is disabled Corresponding interrupt is enabled. SAM9G35 SAM9G35 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 5 ...
Page 97
... SAM9G35 SAM9G35 – – – – – – – – – – NIRQ NFIQ 97 97 ...
Page 98
... Access: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Enable effect Enables corresponding interrupt. SAM9G35 SAM9G35 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 5 4 ...
Page 99
... PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9G35 SAM9G35 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS FIQ 99 99 ...
Page 100
... Access: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Clear effect Clears corresponding interrupt. SAM9G35 SAM9G35 100 100 PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 5 ...
Page 101
... PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9G35 SAM9G35 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS FIQ 101 101 ...
Page 102
... The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. SAM9G35 SAM9G35 102 102 – ...
Page 103
... AIC_FVR in case of a spurious fast interrupt. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep- SIVR SIVR SIVR SIVR AIC Write Protect Mode Register SAM9G35 SAM9G35 103 103 ...
Page 104
... PROT: Protection Mode 0 = The Protection Mode is disabled The Protection Mode is enabled. • GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC The nIRQ and nFIQ lines are tied to their inactive state. SAM9G35 SAM9G35 104 104 – ...
Page 105
... PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9G35 SAM9G35 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS – 105 105 ...
Page 106
... PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Disable effect Disables the Fast Forcing feature on the corresponding interrupt. SAM9G35 SAM9G35 106 106 PID29 PID28 PID27 PID21 PID20 PID19 PID13 ...
Page 107
... PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9G35 SAM9G35 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 SYS – 107 107 ...
Page 108
... Debug Control Register” on page 104 • WPKEY: Write Protect KEY Should be written at value 0x414943 ("AIC" in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAM9G35 SAM9G35 108 108 WPKEY ...
Page 109
... WPVSRC. • WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. Note: Reading AIC_WPSR automatically clears all fields. SAM9G35 SAM9G35 109 109 — ...
Page 110
... SAM9G35 SAM9G35 110 110 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
Page 111
... Either General Reset, Wake-up Reset, Software Reset, User Reset, Watchdog • External Reset Signal Shaping • AMBA – Interfaces to the ARM 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 Reset ™ -compliant Interface ® Advanced Peripheral Bus SAM9G35 SAM9G35 111 111 ...
Page 112
... Crystal Oscil- lator Characteristics in the Electrical Characteristics section of the product documentation. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Con- troller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on. SAM9G35 SAM9G35 112 112 Reset Controller POR ...
Page 113
... Figure 14-2 shows the block diagram of the NRST Manager. RSTC_SR URSTS NRSTL NRST RSTC_MR nrst_out External Reset Timer Slow Clock cycles. This gives the approximate duration of an assertion between 60 μs SAM9G35 SAM9G35 user_reset ERSTL exter_nreset 113 113 ...
Page 114
... Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 14-4 SAM9G35 SAM9G35 114 114 XXX BMS sampling delay = 3 cycles shows how the General Reset affects the reset signals ...
Page 115
... When the Main Supply is detected falling, the reset signals are immediately asserted. This tran- sition is synchronous with the output of the Main Supply POR. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 Startup Time Processor Startup XXX EXTERNAL RESET LENGTH BMS Sampling = 2 cycles SAM9G35 SAM9G35 Any Freq. 0x0 = General Reset XXX 115 115 ...
Page 116
... EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How- ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. SAM9G35 SAM9G35 116 116 Resynch. Processor Startup 2 cycles ...
Page 117
... If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 Resynch. 2 cycles XXX >= EXTERNAL RESET LENGTH SAM9G35 SAM9G35 Processor Startup 0x4 = User Reset 117 117 ...
Page 118
... WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. SAM9G35 SAM9G35 118 118 Resynch. Processor Startup ...
Page 119
... The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 Any Freq. Processor Startup = 3 cycles Any XXX proc_nreset signal. SAM9G35 SAM9G35 0x2 = Watchdog Reset EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 119 119 ...
Page 120
... Reading the RSTC_SR status register resets the URSTS bit . Figure 14-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) SAM9G35 SAM9G35 120 120 read RSTC_SR 2 cycle resynchronization 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 Figure ...
Page 121
... The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write SAM9G35 SAM9G35 Reset Back-up Reset - 0x0000_0001 0x0000_0000 - 0x0000_0000 121 121 ...
Page 122
... If KEY is correct, resets the peripherals. • EXTRST: External Reset effect KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM9G35 SAM9G35 122 122 KEY ...
Page 123
... Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress software command is being performed by the reset controller. The reset controller is ready for a software command software reset command is being performed by the reset controller. The reset controller is busy. SAM9G35 SAM9G35 123 123 – ...
Page 124
... This field defines the external reset length. The external reset is asserted during a time of 2 allows assertion duration to be programmed between 60 μs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM9G35 SAM9G35 124 124 29 28 ...
Page 125
... CPIV 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ® ® /WinCE compliant tick generator ™ -compliant Interface PIT_MR PIV = 0 1 PIT_PIVR PIT_PIIR SAM9G35 SAM9G35 set 0 PIT_SR PITS reset 0 1 12-bit Adder read PIT_PIVR PICNT PICNT PIT_MR PITIEN pit_irq 125 125 ...
Page 126
... PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. SAM9G35 SAM9G35 126 126 Figure 15-2 illustrates 11053B– ...
Page 127
... Figure 15-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler 0 0 SAM9G35 SAM9G35 1 127 127 ...
Page 128
... Periodic Interval Timer (PIT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register SAM9G35 SAM9G35 128 128 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only Reset ...
Page 129
... The bit PITS in PIT_SR has no effect on interrupt The bit PITS in PIT_SR asserts interrupt. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep- – – – – – PIV PIV SAM9G35 SAM9G35 – PITIEN PITEN PIV 129 129 ...
Page 130
... SAM9G35 SAM9G35 – – – – – – – – – – – PITS 130 130 ...
Page 131
... PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep- PICNT CPIV CPIV SAM9G35 SAM9G35 CPIV 131 131 ...
Page 132
... PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. SAM9G35 SAM9G35 132 132 PICNT ...
Page 133
... Time, Date and Alarm 32-bit Parallel Load 16.3 Block Diagram Figure 16-1. RTC Block Diagram Slow Clock: SLCK Bus Interface 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 32768 Divider Time Bus Interface Entry Control SAM9G35 SAM9G35 Date Interrupt RTC Interrupt Control 133 133 ...
Page 134
... Each of these fields can be enabled or disabled to match the alarm condition: • If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled given month, date, hour/minute/second. SAM9G35 SAM9G35 134 134 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
Page 135
... If the 12-hour mode is selected by means of the RTC_MODE register, a 12-hour value can be pro- grammed and the returned value on RTC_TIME will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIME register) to determine the range to be checked. SAM9G35 SAM9G35 135 135 ...
Page 136
... Figure 16-2. Update Sequence SAM9G35 SAM9G35 136 136 Begin Prepare TIme or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR No ACKUPD = 1 ? Yes Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR End Polling or IRQ (if enabled) 11053B– ...
Page 137
... RTC_CALR Read-write RTC_TIMALR Read-write RTC_CALALR Read-write RTC_SR Read-only RTC_SCCR Write-only RTC_IER Write-only RTC_IDR Write-only RTC_IMR Read-only RTC_VER Read-only – – – – SAM9G35 SAM9G35 Reset 0x0 0x0 0x0 0x01210720 0x0 0x01010000 0x0 – – – 0x0 0x0 – – 137 137 ...
Page 138
... The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL Value Name Description 0 WEEK Week change (every Monday at time 00:00:00) 1 MONTH Month change (every 01 of each month at time 00:00:00) 2 YEAR Year change (every January 1 at time 00:00:00) 3 – SAM9G35 SAM9G35 138 138 – – – – – – 13 ...
Page 139
... SAM9G35 SAM9G35 – – – – – – – – – – – HRMOD 139 139 ...
Page 140
... HOUR: Current Hour The range that can be set (BCD) in 12-hour mode (BCD) in 24-hour mode. • AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode AM PM. All non-significant bits read zero. SAM9G35 SAM9G35 140 140 – – ...
Page 141
... The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep- YEAR CENT SAM9G35 SAM9G35 26 25 DATE 18 17 MONTH 141 141 ...
Page 142
... This field is the alarm field corresponding to the BCD-coded hour counter. • AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled The hour-matching alarm is enabled. SAM9G35 SAM9G35 142 142 – ...
Page 143
... The date-matching alarm is enabled. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep- – – – – – – – SAM9G35 SAM9G35 26 25 DATE 18 17 MONTH 10 9 – – – – – 0 – 143 143 ...
Page 144
... No calendar event has occurred since the last clear least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. SAM9G35 SAM9G35 144 144 – ...
Page 145
... CALCLR TIMCLR SAM9G35 SAM9G35 26 25 – – – – – – SECCLR ALRCLR ACKCLR 24 – 16 – 8 – 0 145 145 ...
Page 146
... The second periodic interrupt is enabled. • TIMEN: Time Event Interrupt Enable effect The selected time event interrupt is enabled. • CALEN: Calendar Event Interrupt Enable effect. • The selected calendar event interrupt is enabled. SAM9G35 SAM9G35 146 146 – – ...
Page 147
... CALDIS TIMDIS SAM9G35 SAM9G35 – – – – – – SECDIS ALRDIS ACKDIS – – 8 – 0 147 147 ...
Page 148
... TIM: Time Event Interrupt Mask 0 = The selected time event interrupt is disabled The selected time event interrupt is enabled. • CAL: Calendar Event Interrupt Mask 0 = The selected calendar event interrupt is disabled The selected calendar event interrupt is enabled. SAM9G35 SAM9G35 148 148 – ...
Page 149
... NVCALALR SAM9G35 SAM9G35 26 25 – – – – – – NVTIMALR NVCAL NVTIM 24 – 16 – 8 – 0 149 149 ...
Page 150
... SAM9G35 SAM9G35 150 150 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
Page 151
... Interface ® Advanced Peripheral Bus WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD = 0 set WDUNF reset set WDERR reset SAM9G35 SAM9G35 reload SLCK 1/128 WDT_MR WDRSTEN wdt_fault (to Reset Controller) wdt_int WDFIEN WDT_MR 151 151 ...
Page 152
... If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to the reset controller is deasserted. Writing the WDT_MR reloads and restarts the down counter. SAM9G35 SAM9G35 152 152 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
Page 153
... WDIDLEHLT and WDDBGHLT in the WDT_MR. Figure 17-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault SAM9G35 SAM9G35 153 153 Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN is 0 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
Page 154
... Watchdog Timer (WDT) User Interface Table 17-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register SAM9G35 SAM9G35 154 154 Name Access WDT_CR Write-only WDT_MR Read-write Once WDT_SR Read-only Reset - 0x3FFF_2FFF 0x0000_0000 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
Page 155
... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM9G35 SAM9G35 155 155 KEY – – – ...
Page 156
... The Watchdog stops when the processor is in debug state. • WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. • WDDIS: Watchdog Disable SAM9G35 SAM9G35 156 156 ...
Page 157
... Enables the Watchdog Timer. 1: Disables the Watchdog Timer. SAM9G35 SAM9G35 157 157 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
Page 158
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. SAM9G35 SAM9G35 158 158 – ...
Page 159
... SHDW_SR reset WAKEUP0 SHDW_SR set read SHDW_SR reset SHDW_MR RTTWK SHDW_SR set read SHDW_SR reset SHDW_MR RTCWK SHDW_SR set SAM9G35 SAM9G35 SLCK Wake-up SHDN Shutdown Output Controller SHDW_CR Shutdown SHDW 159 159 ...
Page 160
... The software is able to control the pin (SHDW_CR) with the bit SHDW at 1. The shutdown is taken into account only 2 slow clock cycles after the write of SHDW_CR. This register is password-protected and so the value written SAM9G35 SAM9G35 160 160 read SHDW_SR reset ...
Page 161
... RTC alarm status flag is cleared before shutting down the system.Otherwise, no rising edge of the status flag may be detected and the wake-up fails fail. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 pin is released new input change is detected before the counter reaches the corre- SAM9G35 SAM9G35 161 161 ...
Page 162
... Shutdown Controller (SHDWC) User Interface Table 18-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register SAM9G35 SAM9G35 162 162 Name Access SHDW_CR Write-only SHDW_MR Read-write SHDW_SR Read-only Reset - 0x0000_0003 0x0000_0000 11053B–ATARM–22-Sep-11 ...
Page 163
... KEY – – – – – – – – – pin. SAM9G35 SAM9G35 – – – – – – – – SHDW 163 163 ...
Page 164
... Because of the internal synchronization of WKUP0, the (CPTWK Slow Clock cycles after the event on WKUP. • RTCWKEN: Real-time Clock Wake-up Enable 0 = The RTC Alarm signal has no effect on the Shutdown Controller The RTC Alarm signal forces the de-assertion of the SAM9G35 SAM9G35 164 164 – ...
Page 165
... At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. • RTCWK: Real-time Clock Wake- wake-up alarm from the RTC occurred since the last read of SHDW_SR least one wake-up alarm from the RTC occurred since the last read of SHDW_SR. SAM9G35 SAM9G35 165 165 – ...
Page 166
... SAM9G35 SAM9G35 166 166 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
Page 167
... General Purpose Backup Registers (GPBR) User Interface Table 19-1. Register Mapping Offset Register 0x0 General Purpose Backup Register 0 ... ... 0xc General Purpose Backup Register 3 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 Name SYS_GPBR0 ... SYS_GPBR3 SAM9G35 SAM9G35 Access Reset Read-write – ... ... Read-write – 167 167 ...
Page 168
... General Purpose Backup Register x Name: SYS_GPBRx Address: 0xFFFFFE60 [0], 0xFFFFFE64 [1], 0xFFFFFE68 [2], 0xFFFFFE6C [3] Access: Read-write • GPBR_VALUEx: Value of GPBR x SAM9G35 SAM9G35 168 168 GPBR_VALUEx GPBR_VALUEx GPBR_VALUEx GPBR_VALUEx 11053B–ATARM–22-Sep-11 ...
Page 169
... Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through the Power Management Controller. • Enable the 32,768 Hz oscillator by setting the bit OSC32EN to 1. 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 On Chip RC OSC Slow Clock XIN32 Oscillator XOUT32 SAM9G35 SAM9G35 RCEN Slow Clock SLCK OSCSEL OSC32EN OSC32BYP 169 169 ...
Page 170
... Switch from 32,768 Hz oscillator to internal RC by setting the bit OSCSEL to 0. • Wait 5 slow clock cycles for internal resynchronization. • Disable the 32,768 Hz oscillator by setting the bit OSC32EN to 0. SAM9G35 SAM9G35 170 170 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
Page 171
... Slow Clock Configuration (SCKC) User Interface Table 20-1. Register Mapping Offset Register 0x0 Slow Clock Configuration Register 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 Name Access SCKC_CR Read-write SAM9G35 SAM9G35 Reset 0x0000_0001 171 171 ...
Page 172
... OSCSEL SAM9G35 SAM9G35 26 25 – – – – – – OSC32BYP OSC32EN RCEN 24 – 16 – 8 – 0 172 172 ...
Page 173
... MHz Fast RC Oscillator • PLLACK is the output of the Divider and 400 to 800 MHz programmable PLL (PLLA) • UPLLCK is the output of the 480 MHz UTMI PLL (UPLL) 11053B–ATARM–22-Sep-11 Section 22.13 ”Power Management Controller (PMC) User SAM9G35 Interface”. However, 173 ...
Page 174
... OSC32BYP to accept an external slow clock on XIN32. The internal 32 kHz RC oscillator and the 32,768 Hz oscillator can be enabled by setting to 1, respectively, RCEN bit and OSC32EN bit in the System Controller user interface. The OSCSEL command selects the slow clock source. SAM9G35 174 Clock Generator On Chip ...
Page 175
... Enable the bypass path OSC32BYP bit set to 1. • Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0. 11053B–ATARM–22-Sep-11 Clock Generator On Chip RC OSC Slow Clock XIN32 Oscillator XOUT32 SAM9G35 RCEN Slow Clock SLCK OSCSEL OSC32EN OSC32BYP 175 ...
Page 176
... Switch from 32768 Hz oscillator to internal RC by setting the bit OSCSEL to 0. • Wait 5 slow clock cycles for internal resynchronization. • Disable the 32768 Hz oscillator by setting the bit OSC32EN to 0. • Switch the master clock back to the slow clock domain SAM9G35 176 11053B–ATARM–22-Sep-11 ...
Page 177
... Slow clock is 32768 Hz oscillator 11053B–ATARM–22-Sep- – – – – – – – – – – – OSCSEL SAM9G35 26 25 – – – – – – OSC32BYP OSC32EN RCEN 24 – 16 – 8 – 0 177 ...
Page 178
... The main clock can be generated either by an external 12 MHz crystal oscillator or by the on- chip 12 MHz RC oscillator. This fast RC oscillator allows the processor to start or restart in a few microseconds when 12 MHz internal RC is selected. The 12 MHz crystal oscillator can be bypassed by setting the bit MOSCXTBY to accept an exter- nal main clock on XIN. SAM9G35 178 MOSCRCEN MOSCRCF 12 MHz ...
Page 179
... Crystal Startup Time Wait MOSCRCS = 1 System switches on Main Clock to speed-up the boot System is running at 12 MHz External oscillator is started for better accuracy MOSCXTEN = 1 MOSCSEL = 0 SAM9G35 MOSCRCEN Main Clock MOSCSEL MOSCXTEN MOSCXTBY Wait MOSCXTS = 1 User switches on external oscillator MOSCSEL=1 Wait while MOSCSELS =1 ...
Page 180
... Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) can trigger an interrupt to the processor. 21.6 MHz Crystal Oscillator After reset, the MHz Crystal Oscillator is disabled and it is not selected as the source of MAINCK. SAM9G35 180 11053B–ATARM–22-Sep-11 ...
Page 181
... Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main Clock Frequency Register (CKGR_MCFR) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 11053B–ATARM–22-Sep-11 SAM9G35 181 ...
Page 182
... MAINCK, the 12 MHz frequency must also be selected because the UTMI PLL multiplier contains a built-in multiplier obtain the USB High Speed 480 MHz MHz crystal is needed to use the USB. SAM9G35 182 shows the block diagram of the divider and PLLA block. DIVA ...
Page 183
... The user has to load the number of Slow Clock cycles required to cover the UTMI PLL transient time into the PLLCOUNT field. 11053B–ATARM–22-Sep-11 UPLLEN MAINCK UTMI PLL UPLLCOUNT UTMI PLL SLCK Counter SAM9G35 UPLLCK LOCKU 183 ...
Page 184
... Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery SAM9G35 184 DDR clock is not available when Master Clock (MCK) equals Processor Clock (PCK). ...
Page 185
... This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. Figure 22-1. Master Clock Controller MAINCK PLLACK UPLLCK 11053B–ATARM–22-Sep-11 PMC_MCKR PMC_MCKR CSS SLCK Master Clock Prescaler PRES MCK To the Processor Clock Controller (PCK) SAM9G35 185 ...
Page 186
... Note: The ARM Wait for Interrupt mode is entered by means of CP15 coprocessor operation. Refer to the Atmel application note, Systems, lit. number 6217. When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. SAM9G35 186 USBS USBDIV /1.5 /2 ...
Page 187
... To write the division factor on a particular peripheral, the user needs to write a WRITE command, the peripheral ID and the chosen divi- sion factor. To read the current division factor on a particular peripheral, the user just needs to write the READ command and the peripheral ID. 11053B–ATARM–22-Sep-11 SAM9G35 187 ...
Page 188
... Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register to be set. This can be done either by polling the status register or by wait- ing the interrupt line to be raised if the associated interrupt to MOSCS has been enabled in the PMC_IER register. 2. Setting PLLA and divider: SAM9G35 188 11053B–ATARM–22-Sep-11 ...
Page 189
... The CSS field is used to select the clock source of the Master Clock and Processor Clock dividers. By default, the selected clock source is slow clock. The PRES field is used to control the Master/Processor Clock prescaler. The user can choose between different values ( 16, 32, 64). Prescaler output is the selected 11053B–ATARM–22-Sep-11 write_register(CKGR_PLLAR,0x00040805) SAM9G35 189 ...
Page 190
... The Master Clock is main clock divided by 16. SAM9G35 190 IF PLLA clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLAR, the MCKRDY flag will go low while PLLA is unlocked. Once PLLA is locked again, LOCK goes high and MCKRDY is set ...
Page 191
... Depending on the system used, 19 peripheral clocks can be enabled or disabled. The PMC_PCR provides a clear view as to which peripheral clock is enabled. Note: Code Examples: write_register(PMC_PCER,0x00000110) Peripheral clocks 4 and 8 are enabled. write_register(PMC_PCDR,0x00000010) Peripheral clock 4 is disabled. 11053B–ATARM–22-Sep-11 Each enabled peripheral clock corresponds to Master Clock. SAM9G35 191 ...
Page 192
... Table 22-1. To Main Clock SLCK PLL Clock Notes: Table 22-2. To PLLA Clock UPLL Clock SAM9G35 192 and Table 22-2 give the worst case timings required for the Master Clock to switch Clock Switching Timings (Worst Case) From Main Clock – 0.5 x Main Clock + 4.5 x SLCK ...
Page 193
... Figure 22-3. Switch Master Clock from Slow Clock to PLL Clock Write PMC_MCKR Figure 22-4. Switch Master Clock from Main Clock to Slow Clock Write PMC_MCKR 11053B–ATARM–22-Sep-11 Slow Clock PLL Clock LOCK MCKRDY Master Clock Slow Clock Main Clock MCKRDY Master Clock SAM9G35 193 ...
Page 194
... Figure 22-5. Change PLLA Programming Write CKGR_PLLAR Figure 22-6. Programmable Clock Output Programming Write PMC_PCKx Write PMC_SCER Write PMC_SCDR SAM9G35 194 Slow Clock PLLA Clock LOCKA MCKRDY Master Clock PLL Clock PCKRDY PCKx Output PLL Clock is selected Slow Clock PCKx is enabled PCKx is disabled ...
Page 195
... PMC_IER Write-only PMC_IDR Write-only PMC_SR Read-only PMC_IMR Read-only – – PMC_PLLICPR Write-only – – PMC_WPMR Read-write PMC_WPSR Read-only – – PMC_PCR Read-write SAM9G35 Reset N.A. N.A. 0x0000_0005 N.A. – 0x0000_0000 – 0x1020_0000 0x0100_0008 0x0000_0000 0x0000_3F00 – 0x0000_0001 – 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 – N.A. N.A. ...
Page 196
... No effect Enables the UHP48M and UHP12M OHCI clocks. • UDP: USB Device Clock Enable effect Enables the USB Device clock. • PCKx: Programmable Clock x Output Enable effect Enables the corresponding Programmable Clock output. SAM9G35 196 – – – ...
Page 197
... Disables the corresponding Programmable Clock output. 11053B–ATARM–22-Sep- – – – – – – – – – – SMDCK LCDCK SAM9G35 – – – – – PCK1 PCK0 2 1 DDRCK – PCK – – 197 ...
Page 198
... The UHP48M and UHP12M OHCI clocks are enabled. • UDP: USB Device Port Clock Status 0 = The USB Device clock is disabled The USB Device clock is enabled. • PCKx: Programmable Clock x Output Status 0 = The corresponding Programmable Clock output is disabled The corresponding Programmable Clock output is enabled. SAM9G35 198 – – ...
Page 199
... Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC. 11053B–ATARM–22-Sep- PID29 PID28 PID27 PID21 PID20 PID19 PID13 PID12 PID11 PID5 PID4 PID3 SAM9G35 PID26 PID25 PID24 PID18 PID17 PID16 PID10 PID9 PID8 PID2 - - 199 ...
Page 200
... PID15 PID14 7 6 PID7 PID6 • PIDx: Peripheral Clock x Disable effect Disables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. SAM9G35 200 PID29 PID28 PID27 PID21 PID20 ...