SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 88
SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Memory Management Unit
3.4
3-24
Domain access control
MMU accesses are primarily controlled through the use of domains. There are 16
domains and each has a two-bit field to define access to it. Two types of user are
supported:
•
•
The domains are defined in the domain access control register, CP15 c3. Figure 2-7 on
page 2-18 shows how the 32 bits of the register are allocated to define the 16 two-bit
domains.
Table 3-11 defines how the bits within each domain are interpreted to specify the access
permissions.
Table 3-12 shows how to interpret the Access Permission (AP) bits and how their
interpretation is dependent on the R and S bits (Control Register c1 bits [9:8]).
Value
0 0
0 1
1 0
1 1
Copyright © 2001-2003 ARM Limited. All rights reserved.
clients
managers.
Meaning
No access
Client
Reserved
Manager
Table 3-11 Domain access control register, access control bits
AP
0 0
0 0
0 0
0 0
S
0
1
0
1
Table 3-12 Interpreting access permission (AP) bits
Description
Any access generates a domain fault.
Accesses are checked against the access permission bits in
the section or page descriptor.
Reserved. Currently behaves like the no access mode.
Accesses are not checked against the access permission
bits so a permission fault cannot be generated.
R
0
0
1
1
Privileged permissions
No access
Read-only
Read-only
Unpredictable
User permissions
No access
No access
Read-only
Unpredictable
ARM DDI0198D
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