SAM9R64 Atmel Corporation, SAM9R64 Datasheet - Page 237
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SAM9R64
Manufacturer Part Number
SAM9R64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9R64
Flash (kbytes)
0 Kbytes
Pin Count
144
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
49
Ext Interrupts
49
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
3
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 237 of 284
- Download datasheet (2Mb)
ARM DDI 0029G
•
During RUN-TEST-IDLE, the core is not clocked.
The operation can then be repeated.
Scan chain 1
The primary use for scan chain 1 is for debugging, although it can be used for EXTEST
on the data bus. Scan chain 1 is selected using the SCAN_N TAP controller instruction.
Debugging is similar to INTEST and the procedure described above for scan chain 0
must be followed.
Scan chain 1 is 33 bits long, 32 bits for the data value, plus the scan cell on the
BREAKPT core input. This 33rd bit serves four purposes:
1.
2.
3.
4.
Scan chain 2
Purpose
Length
During UPDATE-DR, the value shifted into the data bus D[31:0] scan cells
appears on the outputs. For all other outputs, the value appears as the data is
shifted round.
Under normal INTEST test conditions, it enables a known value to be scanned
into the BREAKPT input.
During EXTEST test conditions, the value applied to the BREAKPT input from
the system can be captured.
While debugging, the value placed in the 33rd bit determines if the ARM7TDMI
core synchronizes back to system speed before executing the instruction. See
System speed access on page B-31 for further details.
After the ARM7TDMI core has entered debug state, the first time this bit is
captured and scanned out, its value tells the debugger if the core entered debug
state due to a breakpoint, bit 33 clear, or a watchpoint, bit 33 set.
Note
Copyright © 1994-2001. All rights reserved.
Enables the EmbeddedICE macrocell registers to be accessed. The order
of the scan chain, from TDI to TDO is:
1.
2.
See EmbeddedICE block diagram on page B-41.
38 bits.
Read/write, register address bits 4 to 0.
Data value bits 31 to 0.
Debug in Depth
B-19
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