SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 433
SAM9X25
Manufacturer Part Number
SAM9X25
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X25
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
2
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
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- SAM9X25 PDF datasheet #5
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Figure 30-8. Write Command Followed By a Read Command without Burst Write Interrupt, Low-power DDR1-SDRAM
Figure 30-9. Single Write Access Followed By A Read Access Low-power DDR1-SDRAM Devices
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
COMMAND
DQS[1:0]
COMMAND
DM[1:0]
SDCLK
BA[1:0]
D[15:0]
A[12:0]
DQS[1:0]
DM[1:0]
SDCLK
BA[1:0]
D[15:0]
A[12:0]
Device
NOP
0
3
0
3
NOP
In the case of a single write access, write operation should be interrupted by a read access but
DM must be input 1 cycle prior to the read command to avoid writing invalid data. See
9 on page
PRCHG
col a
433.
Row a
NOP
WRITE
ACT
0
Da
Twrd = BL/2 +2 = 8/2 +2 = 6
NOP
Db
Dc
WRITE
Da
Dd De Df
NOP
col a
0
Dg Dh
NOP
3
col a
3
Db
Twr = 1
READ
READ
BST
BST
Data masked
Da Db
Da Db
NOP
SAM9X25
SAM9X25
NOP
Figure 30-
433
433
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