AT32UC3C1512C Automotive Atmel Corporation, AT32UC3C1512C Automotive Datasheet - Page 706
AT32UC3C1512C Automotive
Manufacturer Part Number
AT32UC3C1512C Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.AT32UC3C0512C_AUTOMOTIVE.pdf
(1312 pages)
3.AT32UC3C0512C_AUTOMOTIVE.pdf
(107 pages)
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- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #3
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Figure 27-11. Arbitration Cases
27.8.7
27.8.7.1
9166C–AVR-08/11
Data from a Master
TWI DATA transfer
Data from TWI
(DADR + W + START + Write THR)
Combined Transfers
ARBLST
A transfer is programmed
TWCK
Write Followed by Write
TWD
TWCK
TWD
CMDR and NCMDR may be used to generate longer sequences of connected transfers, since
generation of START and/or STOP conditions is programmable on a per-command basis.
Writing NCMDR with START=1 when the previous transfer was written with STOP=0 will cause
a REPEATED START on the bus. The ability to generate such connected transfers allows arbi-
trary transfer lengths, since it is legal to write CMDR with both START=0 and STOP=0. If this is
done in master receiver mode, the CMDR.ACKLAST bit must also be controlled.
As for single data transfers, the TXRDY and RXRDY bits in the Status Register indicates when
data to transmit can be written to THR, or when received data can be read from RHR. Transfer
of data to THR and from RHR can also be done automatically by DMA, see
Consider the following transfer:
START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+W, DATA+A, DATA+A, STOP.
To generate this transfer:
1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0.
2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0.
3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR.
4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR.
5. Wait until SR.TXRDY==1, then write third data byte to transfer to THR.
S
S
S
1
1
1
Transfer is stopped
0 0
0
0 0
1
1 1
1 1
TWI stops sending data
Arbitration is lost
(DADR + W + START + Write THR)
Transfer is programmed again
Data from the master
Bus is busy
Transfer is kept
P
P
Bus is free
Bus is considered as free
Transfer is initiated
S
S
S
1
1
1
0
0 0
0
1
0
1 1
The master stops sending data
1 1
Arbitration is lost
AT32UC3C
Section 27.8.5
Data from the TWI
706
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