CS181022-CQZ Cirrus Logic Inc, CS181022-CQZ Datasheet - Page 13
![IC COBRANET CS181022 144LQFP](/photos/7/3/70378/cs181022-cqz_sml.jpg)
CS181022-CQZ
Manufacturer Part Number
CS181022-CQZ
Description
IC COBRANET CS181022 144LQFP
Manufacturer
Cirrus Logic Inc
Series
CobraNet®r
Type
Audio Processorr
Specifications of CS181022-CQZ
Package / Case
144-LQFP
Applications
Data Transport
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Number Of Converters
16
Core Size
32 Bit
Digital Ic Case Style
LQFP
No. Of Pins
144
Supply Voltage Range
1.71V To 1.89V
Operating Temperature Range
0°C To +70°C
Filter Terminals
SMD
Supply Voltage Min
3.13V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1021 - MODULE COBRANET 4961 CM2 FB598-1020 - MODULE COBRANET 1810 CM2 MT
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1026
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS181022-CQZ
Manufacturer:
MYSON
Quantity:
320
Company:
Part Number:
CS181022-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Company:
Part Number:
CS181022-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
DAO1_DATA[3:0]
DAI1_DATA[3:0]
4.2.3 Synchronous Serial (Audio) Signals
DAO1_SCLK
4.2.4 Audio Clock Signals
DS651UM23
Version 2.3
DAO1_LRCLK
DAO2_LRCLK
DAI1_SCLK
DAI1_LRCLK
REFCLK_IN
MCLK_OUT
MCLK_IN
Signal
Signal
(FS1)
(FS1)
Audio Input Data
The synchronous serial interfaces are used to bring digital audio into and out of the
system. Typically the synchronous serial is wired to ADCs and/or DACs. Detailed timing
and format is described in
See
*An external multiplexor controlled by this pin is required for full MCLK_IN and MCLK out
implementation.
Audio Bit Clock
Audio Bit Clock
Audio Output
Reference clock
Description
Sample clock
Sample clock
Sample clock
Master audio
Master audio
clock output
Description
clock input
"Synchronization" on page 17
Data
output
output
input
Direction
Direction
Out
Out
In
In
Out
Out
Out
In
In
In
©
A[15:12]
Copyright 2005 Cirrus Logic, Inc.
J3:A18,
"Digital Audio Interface" on page
J3:A7
J4:A7
CM-2
Pin #
B18
J3:
J3:A3
J3:A3
J3:A6
J3:A5
J3:A4
CM-2
Pin #
131, 132, 134, 135
for an overview of synchronization modes and issues.
CS4961xx Pin #
CS4961xx Pin #
CS1810xx/
15-17, 19
CS1810xx/
137
20
138
14
97
22
8*
8*
Synchronous serial bit clock.
64 FS for CS18100x & CS49610x (2x1 channel)
64 FS for CS18101x & CS49611x (2x4
channels)
128 FS for CS18102x & CS49612x (4x4
channels)
Typically tied to DAI1_SCLK.
Output synchronous serial audio data
DAO1_DATA[3:1] not used for CS18100x &
CS49610x.
Input synchronous serial audio data
DAI1_DATA[3:1] not used for CS18100x &
CS49610x.
Should be tied to DAO1_SCLK.
Synchronous serial bit clock.
Should be tied to DAO1_LRCLK for all devices.
FS1 (word clock) for CS18100x/CS49610x and
CS18101x/CS49611x.
FS1 (word clock) for CS18102x & CS49612x.
Clock input for synchronizing network to an
external clock source, for redundancy control
and synchronization of FS divider chain to
external source. See
page 17
For systems featuring multiple CobraNet
interfaces operating off a common master
clock. See
more detail.
Low jitter 24.576 MHz master audio clock.
CobraNet Hardware User’s Manual
for more detail.
19.
"Synchronization" on page 17
Pinout and Signal Descriptions
Notes
Notes
"Synchronization" on
for
13