CS8406-DZZ Cirrus Logic Inc, CS8406-DZZ Datasheet - Page 12

IC XMITTER DGTL 192KHZ 28TSSOP

CS8406-DZZ

Manufacturer Part Number
CS8406-DZZ
Description
IC XMITTER DGTL 192KHZ 28TSSOP
Manufacturer
Cirrus Logic Inc
Type
Digital Audio Interface Transmitterr
Datasheet

Specifications of CS8406-DZZ

Applications
Automotive Audio
Mounting Type
Surface Mount
Package / Case
28-TSSOP
Audio Control Type
Digital
Control Interface
3 Wire, Serial
Control / Process Application
AV & DVD Receivers, CD-R, Digital Mixing Consoles
Supply Voltage Range
3.14V To 5.25V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1017 - BOARD EVAL FOR CS8416 RCVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1722

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS8406-DZZ
Manufacturer:
CIRRUS
Quantity:
20 000
12
4. THREE-WIRE SERIAL INPUT AUDIO PORT
A 3-wire serial audio input port is provided. The interface format can be adjusted to suit the attached device through
the control registers. The following parameters are adjustable:
Figure 7
In Master Mode, the left/right clock and the serial bit clock are outputs, derived from the OMCK input pin master
clock.
In Slave Mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be synchronous to the
OMCK master clock, but the serial bit clock can be asynchronous and discontinuous if required. The left/right clock
should be continuous, but the duty cycle can be less than the specified typical value of 50% if enough serial clocks
are present in each phase to clock all the data bits.
X = don’t care to match format, but does need to be set to the desired setting
+ I²S can accept an arbitrary number of bits, determined by the number of ISCLK cycles
* See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Right Justified
Left Justified
Master or slave
Serial clock frequency
Audio data resolution
Left or right justification of the data relative to left/right clock
Optional one-bit cell delay of the first data bit
Polarity of the bit clock
Polarity of the left/right clock (by setting the appropriate control bits, many formats are possible.)
shows a selection of common input formats with the corresponding control bit settings.
I²S
Left
Justified
(In)
Right
Justified
(In)
I S
(In)
2
ILRCK
ISCLK
SDIN
ILRCK
ISCLK
SDIN
ILRCK
ISCLK
SDIN
SIMS*
X
X
X
LSB
Figure 7. Serial Audio Input Example Formats
MSB
Left
SISF*
MSB
X
X
X
Left
MSB
Left
SIRES[1:0]*
LSB
00+
00+
XX
LSB
LSB
MSB
Right
SIJUST*
Right
MSB
0
0
1
MSB
Right
SIDEL*
LSB
LSB
0
1
0
LSB
MSB
SISPOL*
MSB
0
0
0
CS8406
SILRPOL*
DS580F5
0
1
0

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