CS8427-CSZ Cirrus Logic Inc, CS8427-CSZ Datasheet - Page 55
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CS8427-CSZ
Manufacturer Part Number
CS8427-CSZ
Description
IC TXRX DGTL AUDIO 96KHZ 28SOIC
Manufacturer
Cirrus Logic Inc
Type
Digital Audio Interface Transceiver (DIX)r
Datasheet
1.CS8427-DZZ.pdf
(60 pages)
Specifications of CS8427-CSZ
Applications
Automotive Audio
Mounting Type
Surface Mount
Package / Case
28-SOIC
Audio Control Type
Digital
Control Interface
I2C, Serial
Control / Process Application
AV & DVD Receivers, CD-R, Digital Mixing Consoles
Supply Voltage Range
2.85V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1783 - EVALUATION BOARD FOR CS8427
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1733
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS8427-CSZ
Manufacturer:
CIRRUS
Quantity:
1 370
Part Number:
CS8427-CSZ
Manufacturer:
CIRRUS
Quantity:
20 000
20. APPENDIX C: PLL FILTER
20.1
An on-chip Phase Locked Loop (PLL) is used to re-
cover the clock from the incoming data stream.
Figure 30 is a simplified diagram of the PLL in
these parts. When the PLL is locked to an AES3 in-
put stream, it is updated at each preamble in the
AES3 stream. This occurs at twice the sampling
frequency, F
it is updated at F
doesn’t affect jitter.
There are some applications where low jitter in the
recovered clock, presented on the RMCK pin, is
important. For this reason, the PLL has been de-
signed to have good jitter attenuation characteris-
tics, as shown in Figure 33, Figure 34, Figure 35,
and Figure 36. In addition, the PLL has been de-
DS477F5
General
INPUT
S
. When the PLL is locked to ILRCK,
S
so that the duty cycle of the input
and Charge Pump
Comparator
Phase
÷N
Figure 30. PLL Block Diagram
Cfilt
Rfilt
signed to only use the preambles of the AES3
stream to provide lock update information to the
PLL. This results in the PLL being immune to data
dependent jitter affects because the AES3 pream-
bles do not vary with the data.
The PLL has the ability to lock onto a wide range of
input sample rates with no external component
changes. If the sample rate of the input subse-
quently changes, for example in a varispeed appli-
cation, the PLL will only track up to ±12.5% from
the nominal center sample rate. The nominal cen-
ter sample rate is the sample rate that the PLL first
locks onto upon application of an AES3 data
stream or after enabling the CS8427 clocks by set-
ting the RUN control bit. If the 12.5% sample rate
limit is exceeded, the PLL will return to its wide lock
range mode and re-acquire a new nominal center
sample rate.
Crip
VCO
RMCK
CS8427
55