LT1011AIS8#TR Linear Technology, LT1011AIS8#TR Datasheet - Page 8
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LT1011AIS8#TR
Manufacturer Part Number
LT1011AIS8#TR
Description
IC COMPARATOR VOLTAGE 5V 8SOIC
Manufacturer
Linear Technology
Type
General Purposer
Datasheet
1.LT1011CN8PBF.pdf
(16 pages)
Specifications of LT1011AIS8#TR
Number Of Elements
1
Output Type
Open Collector
Voltage - Supply
3 V ~ 36 V, ±1.5 V ~ 18 V
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
LT1011/LT1011A
APPLICATIONS INFORMATION
The input resistors should limit fault current to a reasonable
value (0.1mA to 20mA). Power dissipation in the resis-
tors must be considered for continuous faults, especially
when the LT1011 supplies are off. One fi nal caution: lightly
loaded supplies may be forced to higher voltages by large
fault currents fl owing through D1-D4.
R3 and R4 limit input current to the LT1011 to less than
1mA when the input signals are held below V
be eliminated if R1 and R2 are large enough to limit fault
current to less than 1mA.
Input Slew Rate Limitations
The response time of a comparator is typically measured
with a 100mV step and a 5mV to 10mV overdrive. Unfor-
tunately, this does not simulate many real world situations
where the step size is typically much larger and overdrive
can be signifi cantly less. In the case of the LT1011, step
size is important because the slew rate of internal nodes
will limit response time for input step sizes larger than
1V. At 5V step size, for instance, response time increases
from 150ns to 360ns. See the curve “Response Time vs
Input Step Size for more detail.
If response time is critical and large input signals are ex-
pected, clamp diodes across the inputs are recommended.
The slew rate limitation can also affect performance when
differential input voltage is low, but both inputs must slew
quickly. Maximum suggested common mode slew rate is
10V/μs.
Strobing
The LT1011 can be strobed by pulling current out of the
STROBE pin. The output transistor is forced to an “off”
state, giving a “hi” output at the collector (Pin 7). Currents
as low as 250μA will cause strobing, but at low strobe
currents, strobe delay will be 200ns to 300ns. If strobe
current is increased to 3mA, strobe delay drops to about
60ns. The voltage at the STROBE pin is about 150mV below
V
strobe current. Do not ground the STROBE pin. It must be
current driven. Figure 4 shows a typical strobe circuit.
Note that there is no bypass capacitor between Pins 5 and
6. This maximizes strobe speed, but leaves the compara-
tor more sensitive to oscillation problems for slow, low
8
+
at zero strobe current and about 2V below V
–
. They may
+
for 3mA
level inputs. A 1pF capacitor between the output and Pin
5 will greatly reduce oscillation problems without reduc-
ing strobe speed.
DC hysteresis can also be added by placing a resistor from
output to Pin 5. See step 5 under “Preventing Oscillation
Problems.”
The pin (6) used for strobing is also one of the offset adjust
pins. Current fl ow into or out of Pin 6 must be kept very
low (< 0.2μA) when not strobing to prevent input offset
voltage shifts.
Output Transistor
The LT1011 output transistor is truly fl oating in the sense
that no current fl ows into or out of either the collector
or emitter when the transistor is in the “off” state. The
equivalent circuit is shown in Figure 5.
0.5mA
I
1
Figure 5. Output Transistor Circuitry
Figure 4. Typical Strobe Circuit
D1
–
+
–15
LT1011
D2
4
15V
V
–
8
6
3k
V
1
+
Q1
7
R1
170Ω
R2
470Ω
TTL OR
CMOS DRIVE
(5V SUPPLY)
5V
R L
OUTPUT
Q2
1011 F04
COLLECTOR
(OUTPUT)
EMITTER
(GND PIN)
OUTPUT
TRANSISTOR
1011 F05
1011afc