EP4CE6E22C8N Altera Corporation, EP4CE6E22C8N Datasheet - Page 41
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EP4CE6E22C8N
Manufacturer Part Number
EP4CE6E22C8N
Description
IC CYCLONE IV FPGA 6K 144EQFP
Manufacturer
Altera Corporation
Series
CYCLONE® IV Er
Datasheet
1.EP4CE15F23C7N.pdf
(44 pages)
Specifications of EP4CE6E22C8N
Number Of Logic Elements/cells
6272
Number Of Labs/clbs
392
Total Ram Bits
276480
Number Of I /o
91
Number Of Gates
-
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP Exposed Pad
Lead Free Status
Lead free
Rohs Status
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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AD
Quantity:
1 200
Company:
Part Number:
EP4CE6E22C8N
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Chapter 1: Cyclone IV Device Datasheet
Glossary
Table 1–46. Glossary (Part 4 of 5)
November 2011 Altera Corporation
Letter
U
T
t
Channel-to-
channel-skew
(TCCS)
t
t
t
t
t
t
Timing Unit
Interval (TUI)
t
t
t
t
t
Transmitter
Output
Waveform
t
t
C
cin
CO
cout
DUTY
FALL
H
INJITTER
OUTJITTER_DEDCLK
OUTJITTER_IO
pllcin
pllcout
RISE
SU
Term
—
High-speed receiver and transmitter input and output clock period.
High-speed I/O block: The timing difference between the fastest and slowest output edges,
including t
Delay from the clock pad to the I/O input register.
Delay from the clock pad to the I/O output.
Delay from the clock pad to the I/O output register.
High-speed I/O block: Duty cycle on high-speed transmitter output clock.
Signal high-to-low transition time (80–20%).
Input register hold time.
High-speed I/O block: The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t
Period jitter on the PLL clock input.
Period jitter on the dedicated clock output driven by a PLL.
Period jitter on the general purpose I/O driven by a PLL.
Delay from the PLL inclk pad to the I/O input register.
Delay from the PLL inclk pad to the I/O output register.
Transmitter output waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O
Standards:
Signal low-to-high transition time (20–80%).
Input register setup time.
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
CO
variation and clock skew. The clock is included in the TCCS measurement.
V os
V
OD
V
OD
Definitions
—
V
OD
Positive Channel (p) = V
Negative Channel (n) = V
Ground
0 V
p - n
Cyclone IV Device Handbook,
C
/w).
OH
OL
Volume 3
1–41