EP4SGX290NF45I3N Altera Corporation, EP4SGX290NF45I3N Datasheet - Page 63
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EP4SGX290NF45I3N
Manufacturer Part Number
EP4SGX290NF45I3N
Description
IC STRATIX IV FPGA 290K 1932FBGA
Manufacturer
Altera Corporation
Series
Stratix® IV GXr
Datasheet
1.EP4SGX70DF29C4N.pdf
(80 pages)
Specifications of EP4SGX290NF45I3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17661952
Number Of I /o
920
Number Of Gates
-
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1932-BBGA
Lead Free Status
Lead free
Rohs Status
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–41. High-Speed I/O Specifications
December 2011 Altera Corporation
TCCS
Receiver
True Differential I/O
Standards -
f
f
DPA Mode
DPA run length
Soft CDR mode
Soft-CDR PPM
tolerance
Non DPA Mode
Sampling Window
Notes to
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4) The maximum ideal frequency is the SERDES factor (J) x the PLL maximum output frequency (f
(5) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
(6) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew
(7) This is achieved by using the LVDS and DPA clock network.
(8) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(9) This only applies to DPA and soft-CDR modes.
(10) This only applies to LVDS source synchronous mode.
HSDRDPA
HSDR
signal integrity simulation is clean.
transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported.
(data rate)
Symbol
Table
(data rate)
1–41:
1
True Differential I/O Standards
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column.
SERDES factor J = 3 to 10
SERDES factor J = 3 to 10
Emulated Differential I/o
Uses an SDR Register
SERDES factor J = 2,
SERDES factor J = 1,
Uses DDR Registers
Conditions
Standards
—
—
—
(Note 1), (2), (10)
–2/–2× Speed Grade
Min
150
—
—
—
—
—
(4)
(4)
(4)
Typ
—
—
—
—
—
—
—
—
—
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
(Part 3 of 3)—Preliminary
10000
1600
Max
100
250
300
300
(4)
(4)
(4)
Min
150
—
—
—
—
—
(4)
(4)
(4)
–3
Speed Grade
OUT
Typ
—
—
—
—
—
—
—
—
—
) provided you can close the design timing and the
10000
1250
Max
100
250
300
300
(4)
(4)
(4)
Min
150
—
—
—
—
—
(4)
(4)
(4)
–4
Speed Grade
Typ
—
—
—
—
—
—
—
—
—
10000
1250
Max
100
250
300
300
(4)
(4)
(4)
1–55
Mbps
Mbps
Mbps
Mbps
PPM
Unit
ps
ps
ps
UI
±