EP4S100G4F45I2 Altera Corporation, EP4S100G4F45I2 Datasheet - Page 6

• Manufacturer Part Number: EP4S100G4F45I2
• Description: IC STRATIX IV FPGA 360K 1932FBGA
• Manufacturer: Altera Corporation
• Series: STRATIX® IV GTr

Specifications of EP4S100G4F45I2

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 23105536
• Number Of I /o: 781
• Number Of Gates: -
• Voltage - Supply: 0.92 V ~ 0.98 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1932-BBGA
• Lead Free Status: Contains lead
• Rohs Status: RoHS non-compliant

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Architecture Features
Stratix IV Device Handbook Volume 1
High-Speed Transceiver Features
1
The Stratix IV device family features are divided into high-speed transceiver features
and FPGA fabric and I/O features.
The high-speed transceiver features apply only to Stratix IV GX and Stratix IV GT
devices.
The following sections describe high-speed transceiver features for Stratix IV GX and
GT devices.
Highest Aggregate Data Bandwidth
Up to 48 full-duplex transceiver channels supporting data rates up to 8.5 Gbps in
Stratix IV GX devices and up to 11.3 Gbps in Stratix IV GT devices.
Wide Range of Protocol Support
Physical layer support for the following serial protocols:
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Stratix IV GX—PCIe Gen1 and Gen2, GbE, Serial RapidIO, SONET/SDH,
XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, GPON,
SAS/SATA, HyperTransport 1.0 and 3.0, and Interlaken
Stratix IV GT—40G/100G Ethernet, SFI-S, Interlaken, SFI-5.1, Serial RapidIO,
SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, 3G-SDI, and Fibre Channel
Extremely flexible and easy-to-configure transceiver data path to implement
proprietary protocols
PCIe Support
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Complete PCIe Gen1 and Gen2 protocol stack solution compliant to PCI
Express base specification 2.0 that includes PHY-MAC, Data Link, and
transaction layer circuitry embedded in PCI Express hard IP blocks
Root complex and end-point applications
x1, x4, and x8 lane configurations
PIPE 2.0-compliant interface
Embedded circuitry to switch between Gen1 and Gen2 data rates
Built-in circuitry for electrical idle generation and detection, receiver detect,
power state transitions, lane reversal, and polarity inversion
8B/10B encoder and decoder, receiver synchronization state machine, and
± 300 parts per million (ppm) clock compensation circuitry
Transaction layer support for up to two virtual channels (VCs)
For more information, refer to the
PCI Express Compiler User
Chapter 1: Overview for the Stratix IV Device Family
June 2011 Altera Corporation
Guide.
Architecture Features