DS28EC20 Maxim, DS28EC20 Datasheet - Page 24

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DS28EC20

Manufacturer Part Number
DS28EC20
Description
The DS28EC20 is a 20480-bit, 1-Wire® EEPROM organized as 80 memory pages of 256 bits each
Manufacturer
Maxim
Datasheet

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CRC GENERATION
The DS28EC20 uses two different types of CRCs. One CRC is an 8-bit type and is stored in the most significant
byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and
compare it to the value stored within the DS28EC20 to determine if the ROM data has been received error-free.
The equivalent polynomial function of this CRC is X
(noninverted) form. It is computed at the factory and programmed into the ROM.
The other CRC is a 16-bit type, generated according to the standardized CRC16 polynomial function
X
scratchpad and with the Extended Read Memory command. In contrast to the 8-bit CRC, the 16-bit CRC is always
communicated in the inverted form. A CRC generator inside the DS28EC20 (Figure 13) calculates a new 16-bit
CRC, as shown in the command flowchart (Figure 7). The bus master compares the CRC value read from the
device to the one it calculates from the data, and decides whether to continue with an operation or to reread the
portion of the data with the CRC error.
With the Write Scratchpad command, the CRC is generated by first clearing the CRC generator and then shifting in
the command code, the target addresses TA1 and TA2, and all the data bytes as they were sent by the bus
master. The DS28EC20 transmits this CRC only if the data bytes written to the scratchpad include scratchpad
ending offset 11111b. The data can start at any location within the scratchpad.
With the Read Scratchpad command, the CRC is generated by first clearing the CRC generator and then shifting in
the command code, the target addresses TA1 and TA2, the E/S byte, and the scratchpad data as they were sent
by the DS28EC20 starting at the target address. The DS28EC20 transmits this CRC only if the reading continues
through the end of the scratchpad, regardless of the actual ending offset.
With the initial pass through the extended read memory flow, the 16-bit CRC value is the result of shifting the
command byte into the cleared CRC generator, followed by the two address bytes and the data bytes. Subsequent
passes through the extended read memory flow generate a 16-bit CRC that is the result of clearing the CRC
generator and then shifting in the data bytes. For more information on generating CRC values refer to Application
Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products
ic.com/AN27).
Figure 13. CRC16 Hardware Description and Polynomial
16
X
X
+ X
0
8
STAGE
STAGE
9
1
15
st
th
+ X
X
X
2
9
1
STAGE
STAGE
+ 1. This CRC is used for fast verification of a data transfer when writing to or reading from the
10
2
nd
th
X
10
STAGE
11
th
X
11
STAGE
X
12
2
STAGE
th
3
Polynomial = X
rd
X
12
STAGE
X
13
3
STAGE
th
4
th
X
13
24 of 27
STAGE
X
8
16
14
4
STAGE
+ X
th
+ X
5
th
X
5
15
14
+ X
+ X
STAGE
X
15
5
STAGE
4
2
th
+ 1
+ 1. This 8-bit CRC is received in the true
6
th
INPUT DATA
X
6
STAGE
7
DS28EC20: 20Kb 1-Wire EEPROM
th
X
X
15
7
STAGE
STAGE
16
8
th
th
X
16
(www.maxim-
CRC
OUTPUT

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