DS1341 Maxim, DS1341 Datasheet
DS1341
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DS1341 Summary of contents
Page 1
... The DS1341/DS1342 also include an input for synchroni- zation. When a reference clock (e.g., 60Hz power line or GPS 1PPS) is present at the CLKIN pin and the enable external clock input bit (ECLK) is set to 1, the DS1341/ DS1342 RTCs are frequency-locked to the external clock and the clock accuracy is determined by the external source ...
Page 2
... DC ELECTRICAL CHARACTERISTICS (V = +1.8V to +5.5V -40NC to +85NC, unless otherwise noted.) (Note PARAMETER SYMBOL Operating Voltage Range Minimum Timekeeping Voltage V Timekeeping Current: DS1341 CLKIN = GND or CLKIN = V CC (Note 4) Timekeeping Current: DS1342 CLKIN = GND or CLKIN = V CC (Note 4) Logic 1 Input Logic 0 Input Input Leakage (SCL, CLKIN/INTA) ...
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... HIGH (Notes 8, 9) HD:DAT (Note 10) SU:DAT t SU:STA t (Note 11 (Note 11) F SU:STO C (Note 11 (Note 12) I/O t (Note 12 (Note 13) OSF (Note 14) CONDITIONS f O ESR DS1341 C L DS1342 MIN TYP MAX UNITS 400 kHz 1.3 Fs 0.6 Fs 1 0.9 Fs 100 ns 0 300 ns 0. 300 ns 0 ...
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... CC CCMAX Note 14: The DS1341/DS1342 can detect any single SCL clock held low longer than t in reset state and can receive a new START condition when SCL is held low for at least t detects this condition, the SDA output is released. The oscillator must be running for this function to work. ...
Page 5
... SQW/INTB OUTPUT-VOLTAGE HIGH vs. OUTPUT CURRENT 2 +1.8V +25° 1.8 1.6 1.4 1.2 1.0 0.8 - OUTPUT CURRENT (mA RTCs for High-ESR Crystals Typical Operating Characteristics DS1341 I 550 500 450 400 +25°C 350 300 250 -40°C 200 4 5 DS1342 I 550 500 450 +85°C 400 350 300 250 200 ...
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... Exposed Pad (TDFN Only). Connect to GND or leave unconnected RTCs for High-ESR Crystals SQW/INTB DS1341 6 SCL DS1342 5 SDA µ SOP FUNCTION Pin Configurations DS1341 DS1342 TDFN Pin Description ) of 6pF (DS1341 serial interface. The SDA pin is ...
Page 7
... The DS1341/DS1342 also accept an external clock reference for synchronization. The external clock can be a 32.768kHz, 50Hz, 60Hz, or 1Hz source. When the enable oscillator bit (EOSC the DS1341/DS1342 use the oscillator for timekeeping. If the enable external clock input bit (ECLK) is set to 1, the time base derived from the oscillator is compared to the 1Hz signal that is derived from the CLKIN signal ...
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Low-Current I External Synchronization When an external clock reference is used, the input from CLKIN/INTA is divided down to 1Hz by the divi- sor selected by the CLKSEL[2:1] bits. The 1Hz from the divider (Ext-1Hz, see the Functional Diagram) ...
Page 9
... ECLK bit is set. The external clock reference must be within the defined frequency tolerance prior to initializing the LOS flag. Table 1 shows the map for the DS1341/DS1342 regis- ters. During a multibyte access, if the address pointer reaches the end of the register space (0Fh), it wraps around to location 00h ...
Page 10
... Years register rolls over from 99 to 00. Illogical time and date entries result in an unde- fined operation. The DS1341/DS1342 can be run in either 12hr or 24hr mode. Bit 6 of the Hours register is defined as the 12hr or 24hr mode select bit. When high, the 12hr mode is selected ...
Page 11
Low-Current I When the RTC register values match alarm register set- tings, the corresponding alarm flag bit (A1F or A2F) is set the Control/Status register. If the correspond- ing alarm interrupt enable bit (A1IE or A2IE) is ...
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Low-Current I BIT 7 BIT 6 OSF DOSF 1 0 Control/Status Register (0Fh) Bit 7: Oscillator Stop Flag (OSF). If the OSF bit that indicates the oscillator has stopped or was stopped for some period of ...
Page 13
... Low-Current Serial Port Operation I The DS1341/DS1342s’ slave address byte is D0h. The first byte sent to the device includes the device identifier and the R/W bit (Figure 5). The device address sent by 2 the I C master must match the address assigned to the device ...
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... D0h), the master is indicating it writes data to the slave (D1h in this case), the master is indi- cating it wants to read from the slave incorrect slave address is written, the DS1341/DS1342 assume the master is communicating with another I and ignore the communication until the next START condition is sent ...
Page 15
... SDA is released and allowed to be pulled high by the external pullup resistor. For the timeout function to work, the oscillator must be enabled and running. Applications Information Power-Supply Decoupling To achieve the best results when using the DS1341/ DS1342, decouple the V power supply with a 0.01FF CC and/or 0.1FF capacitor. Use a high-quality, ceramic, sur- face-mount capacitor if possible ...
Page 16
... Clock and Calendar (00h–06h) section Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...