DS1371 Maxim, DS1371 Datasheet
DS1371
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DS1371 Summary of contents
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... General Description The DS1371 is a 32-bit binary counter that is designed to continuously count time in seconds. An additional counter that can generate a periodic alarm or serve as a watchdog timer is also provided. If enabled as a watchdog timer, the watchdog strobe input pin provides a hardware reset of the counter. If disabled, this counter can be used as 3 Bytes of general- purpose RAM ...
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... 0. (Note 5) CCA I (Notes 6, 7) OSC0 I (Notes 6, 7) OSC1 I (Note 6) DDR TYP MAX UNITS 3 MIN TYP MAX UNITS 1.7 5.5 1.3 5 3.0 3.0 250 100 150 800 1300 100 DS1371 +0.5V μA μ μA μ ...
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... Note 11: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V bridge the undefined region of the falling edge of SCL. Note 12: The maximum t has only to be met if the device does not stretch the LOW period (t HD:DAT Note 13: C — ...
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Typical Operating Characteristics (V = 3.3V +25°C, unless otherwise noted 600 550 500 450 400 350 300 1.5 2.0 2.5 I OSC0 750 700 650 600 550 500 -40 -20 I OSC0 ...
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... Figure 1. Timing Diagram X1 X2 Oscillator V CC Power GND WDS SDA Interface SCL Figure 2. Functional Diagram 32,768Hz 8192Hz 4096Hz 1Hz ÷4 ÷2 ÷4096 DS1371 1Hz WACE Alarm/ 4096Hz M Watchdog 1Hz U ÷4096 X WD/ALM Stat/Ctrl SQW/ INT U SQW CLR ...
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... Oscillator Circuit The DS1371 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate (Figure 2). Table 1 specifies several crystal parameters for the external crystal. Using a crystal with the specified characteristics, the startup time is usually less than one second. ...
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Table 1. Crystal Specifications PARAMETER Nominal Frequency Series Resistance Load Capacitance *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. LOCAL ...
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... Address Map Table 2 shows the address map for the registers of the DS1371. During a multibyte access, when the address pointer reaches the end of the register space (08h), it wraps around to location 00h START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers ...
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Time-of-Day Counter The time-of-day counter is a 32-bit up counter. The contents can be read or written by accessing the address range 00h–03h. When the counter is read, the current time of day is latched into a register, which is ...
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... Bit 7: Enable Oscillator (EOSC). When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is stopped. When this bit is set to a logic 1, the oscillator is stopped and the DS1371 is placed into a low-power standby mode (I Bit 6: WD/ALM Counter Enable (WACE). When set to logic 1, the WD/ALM counter is enabled. ...
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... SQW/INT pin pulses low for 250ms when the WD/ALM counter reaches 0 and sets the completion of the 250ms pulse, the DS1371 clears the AF bit the 250ms pulse is active, writing does not truncate the pulse. ...
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Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed ...
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... Slave transmitter mode (DS1371 read mode). The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1371 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. ...
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... XXXXXXXX DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE); NOTE: LAST DATA BYTE IS FOLLOWED BY A NOT ACKNOWLEDGE (A) SIGNAL) <Slave Address> Sr 1101000 1 A <Data(n+2)> <Data(n+X)> A ... XXXXXXXX A P DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE); NOTE: LAST DATA BYTE IS FOLLOWED BY A NOT ACKNOWLEDGE (A) SIGNAL <Data(n+X)> DS1371 ...
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... The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. DESCRIPTION Serial Interface section (formerly 2-Wire Serial Interface), added text 2 C modes. max from 50nA to 100nA. DDR 2 C read and write protocol figures © 2007 Maxim Integrated Products DS1371 ...