DS1642 Maxim, DS1642 Datasheet - Page 5
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DS1642
Manufacturer Part Number
DS1642
Description
The DS1642 is a 2k x 8 nonvolatile static RAM and a full-function real-time clock (RTC), both of which are accessible in a bytewide format
Manufacturer
Maxim
Datasheet
1.DS1642.pdf
(13 pages)
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RETRIEVING DATA FROM RAM OR CLOCK
The DS1642 is in the read mode whenever
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within t
and
available at the latter of chip enable access (t
data input/output pins (DQ) is controlled by
lines are driven to an intermediate state until t
remain valid, output data will remain valid for output data hold time (t
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1642 is in the write mode whenever
referenced to the latter occurring transition of
the cycle.
write cycle. Data in must be valid t
typical application, the
that care is taken with the data bus to avoid bus contention. If
the data bus can become active with read data defined by the address inputs. A low transition on
then disable the outputs t
DATA RETENTION MODE
When V
or write cycles. However, when V
occurs) the internal clock registers and RAM is blocked from access. This is accomplished internally by
inhibiting access via the
input is switched from the V
maintained from the battery until V
BATTERY LONGEVITY
The DS1642 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the V
is sufficient to power the DS1642 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25C with the internal clock oscillator running in
the absence of V
source disconnected, guaranteeing full energy capacity. When V
V
DS1642 will be much longer than 10 years since no lithium battery energy is consumed when V
present.
PF
, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
OE
CC
access times and states are satisfied. If
CE
is within nominal limits (V
or
CC
WE
power. Each DS1642 is shipped from Dallas Semiconductor with its lithium energy
must return inactive for a minimum of t
OE
WEZ
CE
signal will be high during a write cycle. However,
after
signal. When V
CC
pin to the internal battery and clock activity, RAM, and clock data are
WE
CC
CC
DS
CC
is returned to nominal level.
CC
is below the power-fail point V
goes active.
prior to the end of write and remain valid for t
supply is not present. The capability of this internal power supply
> 4.5V) the DS1642 can be accessed as described above by read
WE
AA
CC
CE
WE
CEA
after the last address input is stable, providing that the
WE
AA
falls below the level of the internal battery supply, power
(write enable) is high, and
) or at output enable access time (t
and
CE
5 of 13
. If the address inputs are changed while
and
or
or
OE
CE
CE
OE
. If the outputs are activated before t
. The addresses must be held valid throughout
are in their active state. The start of a write is
access times are not met, valid data will be
WR
OE
CC
prior to the initiation of another read or
is low prior to
is first applied at a level greater than
PF
OH
(point at which write protection
) but will then go indeterminate
CE
OE
(chip enable) is low. The
can be active provided
WE
OEA
DH
). The state of the
transitioning low
afterward. In a
CE
AA
, the data
WE
and
DS1642
CC
will
CE
OE
is