DS1672 Maxim, DS1672 Datasheet - Page 9

• Manufacturer Part Number: DS1672
• Description: The DS1672 low-voltage serial timekeeping chip incorporates a 32-bit counter and power-monitoring functions
• Manufacturer: Maxim

trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit may result in the clock running fast. Refer to Application
Note 5: “Crystal Considerations with Dallas Real-Time Clocks” for detailed information.
Address Map
The counter is accessed by reading or writing the first 4 bytes of the DS1672 (00h–03h). The control
register and trickle charger are accessed by reading or writing the appropriate register bytes as illustrated
in Table 2. If the master continues to send or request more data after the address pointer has reached 05h,
the address pointer will wrap around to location 00h.
Table 2. Registers
Power Control
The device is fully accessible and data can be written and ready only when V
However, when V
are blocked from any access. If V
V
V
the V
Table 3. Power Control
Oscillator Control
The EOSC bit (bit 7 of the control register) controls the oscillator when in back-up mode. This bit when
set to logic 0 will start the oscillator. When this bit is set to a logic 1, the oscillator is stopped and the
DS1672 is placed into a low-power standby mode (I
powered by V
is incremented only when EOSC is a logic 0.
Microprocessor Monitor
A temperature-compensated comparator circuit monitors the level of V
fail trip point, the RST signal (open drain) is pulled active, and read/write access is inhibited. When V
returns to nominal levels, the RST signal is kept in the active state for t
supply and microprocessor to stabilize. Note, however, that if the EOSC bit is set to a logic 1 (to disable
the oscillator during write protection), the reset signal will be kept in an active state for t
startup time of the oscillator.
V
V
V
V
ADDRESS
BACKUP
CC
SUPPLY CONDITION
CC
CC
CC
CC
to V
00h
01h
02h
03h
04h
05h
BACKUP
< V
< V
> V
> V
when V
BACKUP
PF
PF
PF
PF
, V
, V
, V
, V
source until V
CC,
CC
CC
CC
CC
EOSC
MSB
TCS
B7
when V
CC
the oscillator is always on regardless of the status of the EOSC bit; however, the counter
< V
> V
< V
> V
CC
drops below V
BACKUP
BACKUP
BACKUP
BACKUP
falls below V
TCS
CC
B6
CC
drops below V
is returned to nominal levels (see Table 3).
READ/WRITE
TCS
B5
ACCESS
PF
PF
PF
, (point at which write protection occurs) the internal clock registers
. If V
Yes
Yes
No
No
is less than V
TCS
B4
PF
BACKUP
is greater than V
. Oscillator and counter operation are maintained from
9 of 15
Inactive
Inactive
DS
B3
Active
Active
BACKUP
BACKUP
RST
) when in back-up mode. When the DS1672 is
, the device power is switched from V
DS
B2
BACKUP
POWERED BY
V
BACKUP
, the device power is switched from
V
V
V
RS
B1
CC
CC
CC
CC
RPU
. When V
(typically) to allow the power
LSB
RS
B0
CC
CC
is greater than V
Counter Byte 1
Counter Byte 2
Counter Byte 3
Counter Byte 4
Control
Trickle Charger
falls to the power-
FUNCTION
RPU
plus the
DS1672
CC
PF
CC
to
.