DS3231 Maxim, DS3231 Datasheet - Page 16

no-image

DS3231

Manufacturer Part Number
DS3231
Description
The DS3231 is a low-cost, extremely accurate I²C real-time clock (RTC) with an integrated temperature-compensated crystal oscillator (TCXO) and crystal
Manufacturer
Maxim
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3231
Manufacturer:
DALLAS
Quantity:
20 000
Part Number:
DS3231M
Manufacturer:
DALLAS
Quantity:
20 000
Part Number:
DS3231M+T
Manufacturer:
MAXIM/美信
Quantity:
20 000
Part Number:
DS3231M+TRL
Manufacturer:
MAXIM
Quantity:
28
Part Number:
DS3231M+TRL
Manufacturer:
MAXIM
Quantity:
5
Part Number:
DS3231M+TRL
Manufacturer:
MAXIM/美信
Quantity:
20 000
Part Number:
DS3231MZ
Manufacturer:
DALLAS
Quantity:
20 000
Part Number:
DS3231MZ+
Manufacturer:
Maxim
Quantity:
91
Part Number:
DS3231MZ+TRL
Manufacturer:
MAXIM
Quantity:
14
Part Number:
DS3231MZ+TRL
Manufacturer:
MAXIM
Quantity:
250
Part Number:
DS3231MZ+TRL
Manufacturer:
MAXIM
Quantity:
300
Part Number:
DS3231MZ+TRL
Manufacturer:
MAXIM
Quantity:
5 000
Part Number:
DS3231MZ+TRL
0
Company:
Part Number:
DS3231N
Quantity:
3 400
Part Number:
DS3231S
Manufacturer:
MAXIM
Quantity:
225
Part Number:
DS3231S
Manufacturer:
MAXIM
Quantity:
18 500
Extremely Accurate I
RTC/TCXO/Crystal
Figures 3 and 4 detail how data transfer is accom-
plished on the I
the R/W bit, two types of data transfer are possible:
Figure 2. I
Figure 3. Data Write—Slave Receiver Mode
Figure 4. Data Read—Slave Transmitter Mode
16
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
SDA
SCL
____________________________________________________________________
2
IDLE
C Data Transfer Overview
S - START
A - ACKNOWLEDGE (ACK)
P - STOP
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
S - START
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
S
S
CONDITION
START
ADDRESS>
ADDRESS>
1101000
1101000
<SLAVE
<SLAVE
2
C bus. Depending upon the state of
ADDRESS
MSB FIRST
SLAVE
0
1
<R/W>
<R/W>
1–7
A
A
<WORD ADDRESS (n)>
MASTER TO SLAVE
XXXXXXXX
<DATA (n)>
XXXXXXXX
SLAVE TO MASTER
R/W
8
ACK
9
A
A
<DATA (n + 1)>
SLAVE TO MASTER
MSB
XXXXXXXX
XXXXXXXX
<DATA (n)>
1–7
REPEATED IF MORE BYTES
2
MASTER TO SLAVE
ARE TRANSFERRED
C-Integrated
DATA
LSB
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
8
A
A
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte. Data is transferred with the most
significant bit (MSB) first.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
(X + 1 BYTES + ACKNOWLEDGE)
(X + 1 BYTES + ACKNOWLEDGE)
ACK
<DATA (n + 2)>
<DATA (n + 1)>
9
XXXXXXXX
XXXXXXXX
DATA TRANSFERRED
DATA TRANSFERRED
MSB
1–7
A
A
DATA
...
...
LSB
<DATA (n + X)>
8
<DATA (n + X)
XXXXXXXX
XXXXXXXX
NACK
ACK/
9
STOP CONDITION
REPEATED START
A
A
P
P

Related parts for DS3231