DS5002 Maxim, DS5002 Datasheet
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DS5002
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DS5002 Summary of contents
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... GENERAL DESCRIPTION The DS5002FP secure microprocessor chip is a secure version of the DS5001FP microprocessor chip. In addition to the memory and I/O enhancements of the DS5001FP, the secure microprocessor chip incorporates sophisticated security features available in any processor. The security features of the DS5002FP include an array of mechanisms that are designed to resist all levels of threat, including observation, analysis, and physical attack ...
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... ELECTRICAL SPECIFICATIONS The DS5002FP adheres to all AC and DC electrical specifications published for the DS5001FP. ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………………….-0. Voltage Range on V Relative to Ground… ...
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... Stop mode I is measured with all output pins disconnected; PORT0 = V STOP Note 5: Pin capacitance is measured with a test frequency: 1MHz, T Note the maximum average operating current that can be drawn from V CCO1 Note the current drawn from V LI should be ≤ BAT ...
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AC CHARACTERISTICS—EXPANDED BUS MODE TIMING SPECIFICATIONS ( ±10 0°C to +70°C PARAMETER 1 Oscillator Frequency 2 ALE Pulse Width 3 Address Valid to ALE Low 4 Address Hold After ALE Low 14 RD ...
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Figure 2. Expanded Data Memory Write Cycle AC CHARACTERISTICS—EXTERNAL CLOCK DRIVE ( ± 10 0°C to +70°C PARAMETER 28 External Clock High Time 29 External Clock Low Time 30 External Clock Rise Time ...
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AC CHARACTERISTICS—POWER CYCLE TIME ( ±10 0°C to +70°C PARAMETER 32 Slew Rate from CCMIN 33 Crystal Startup Time 34 Power-on Reset Delay Figure 4. Power Cycle Timing (Figure 4) ...
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AC CHARACTERISTICS—SERIAL PORT TIMING, MODE ±10 0°C to +70°C PARAMETER 35 Serial Port Clock Cycle Time 36 Output Data Setup to Rising Clock Edge 37 Output Data Hold after Rising Clock ...
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AC CHARACTERISTICS—BYTE-WIDE ADDRESS/DATA BUS TIMING ( ±10 0°C to +70°C PARAMETER Delay to Byte-Wide Address Valid from CE1 , 40 CE2 , or CE1N Low During Op Code Fetch Pulse Width of CE ...
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RPC AC CHARACTERISTICS, DBB READ ( ±10 0°C to +70°C PARAMETER Setup Hold After Pulse Width ...
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Figure 7. RPC Timing Mode ...
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PIN DESCRIPTION PIN NAME 11 General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1. It requires 1, 79, 77, P0.0–P0.7 external pullups. Port 0 is also the multiplexed expanded address/data bus. When ...
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... Memory Select. This signal controls the memory size selection. When MSEL = +5V, the 14 MSEL DS5002FP expects to use 32k x 8 SRAMs. When MSEL = 0V, the DS5002FP expects to use a 128k x 8 SRAM. MSEL must be connected regardless of partition, mode, etc. Self-Destruct Input. An active high on this pin causes an unlock procedure. This results in ...
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... DS5002FP are available that incorporate a one-of-a-kind encryption algorithm. When implemented as a part of a secure system design, a system based on the DS5002FP can typically provide a level of security that requires more time and resources to defeat than it is worth to unauthorized individuals who have reason to try ...
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Figure 8. Block Diagram ...
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... Set security lock 5) Exit loader Loading of application software into the program/data RAM is performed while the DS5002FP is in its bootstrap load mode. Loading is only possible when the security lock is clear. If the security lock has previously set, then it must be cleared by issuing the “Z” command from the bootstrap loader. Resetting the security lock instantly clears the previous key word and the contents of the Vector RAM. In addition, the bootstrap ROM writes 0’ ...
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... When the application software is executed, the internal CPU of the DS5002FP operates as normal. Logical addresses are calculated for op code fetch cycles and also data read and write operations. The DS5002FP has the ability to perform address encryption on logical addresses as they are generated internally during the normal course of program execution ...
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... The DS5002FP provides a key management system, which is greatly improved over the DS5000FP. The DS5002FP does not give the user the ability to select a key. Instead, when the loader is given certain commands, the key is set based on the value read from an on-chip hardware random number generator. This action is performed just prior to actually loading the code into the external RAM ...
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... Any read or write operation to the DS5002FP’s external program/data SRAM can only take place if the security lock bit cleared state. Therefore, the first step in loading a program should be the clearing of the security lock bit through the “ ...
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... MEMORY ORGANIZATION Figure 10 illustrates the memory map accessed by the DS5002FP. The entire 64k of program and 64k of data are potentially available to the byte-wide bus. This preserves the I/O ports for application use. The user controls the portion of memory that is actually mapped to the byte-wide bus by selecting the program range and data range. ...
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The memory map and its controls are covered in detail in the Secure Microcontroller User’s Guide. Figure 10. Memory Map in Nonpartitionable Mode ( ...
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Figure 11. Memory Map In Partitionable Mode ( Figure 12. Memory Map with PES = ...
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Figure 13 illustrates a typical memory connection for a system using a 128kB SRAM. Note that in this configuration, both program and data are stored in a common RAM chip. SRAMs. The byte-wide address bus connects to the SRAM address ...
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... This drop varies depending on the load. Low-power SRAMs should be used for this reason. When using the DS5002FP, the user must select the appropriate battery to match the RAM data retention current and the desired backup lifetime. Note that the lithium cell is only loaded when V Secure Microcontroller User’ ...
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... SELECTOR GUIDE STANDARD Pb-FREE/RoHS PART COMPLIANT DS5002FP-16 DS5002FP-16+ DS5002FPM-16 DS5002FPM-16+ DS5002FP-16N DS5002FP-16N+ DS5002FMN-16 DS5002FMN-16+ PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) MM DIM MIN A — ...
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... V . PCN No. (D72502). OL2 OL1 + 0.5V. CC specification and t from 10ns to 0ns. CEHDV specifications to reflect 0.45V internal voltage drop instead of 0.35V. CCO1 © 2006 Maxim Integrated Products DS5002FP Secure Microprocessor Chip MAX (in active mode) from 2µs to 1.3µs. This SPR ...