DS80C390 Maxim, DS80C390 Datasheet
DS80C390
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DS80C390 Summary of contents
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... CAN 2.0B controllers. The redesigned processor core instructions faster than the original for the same crystal speed. The DS80C390 supports a maximum crystal speed of 40MHz, resulting in apparent execution speeds (approximately 2.5X). An optional internal frequency multiplier allows the microprocessor to operate at full speed with a reduced crystal frequency, reducing EMI ...
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... Note 8: set to 1. This is only the current required to hold the low level; transitions from I/O pin also have to overcome the transition current. Ports 1(in I/O mode and 5 source transition current when being pulled down externally. It reaches its maximum at Note 9: approximately 2V. ...
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AC ELECTRICAL CHARACTERISTICS—(MULTIPLEXED ADDRESS/DATA BUS) (Note 10, Note 11) PARAMETER Oscillator Frequency ALE Pulse Width Port 0 Instruction Address or CE0–4 Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In ALE Low to PSEN ...
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... AC SYMBOLS The DS80C390 uses timing parameters and symbols similar to the original 8051 family. The following list of timing symbols is provided as an aid to understanding the timing diagrams. Figure 1. Multiplexed External Program Memory Read Cycle SYMBOL FUNCTION t Time A Address C Clock CE Chip Enable D Input Data ...
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MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 12) PARAMETER MOVX ALE Pulse Width Port 0 MOVX Address, CE0–4, PCE0–4 Valid to ALE Low Address Hold After MOVX Read/Write RD Pulse Width WR Pulse Width RD Low to Valid Data In Data ...
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Figure 2. Multiplexed 9-Cycle Address/Data CE0-3 MOVX Read/Write Operation ...
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Figure 3. Multiplexed 9-Cycle Address/Data PCE0-3 MOVX Read/Write Operation ...
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Figure 4. Multiplexed 2-Cycle Data Memory PCE0-3 Read or Write Figure 5. Multiplexed 2-Cycle Data Memory CE0-3 Read ...
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Figure 6. Multiplexed 2-Cycle Data Memory CE0-3 Write Figure 7. Multiplexed 3-Cycle Data Memory PCE0-3 Read or Write ...
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Figure 8. Multiplexed 3-Cycle Data Memory CE0-3 Read Figure 9. Multiplexed 3-Cycle Data Memory CE0-3 Write ...
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Figure 10. Multiplexed 9-Cycle Data Memory PEC0-3 Read or Write Figure 11. Multiplexed 9-Cycle Data Memory CE0-3 Read ...
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Figure 12. Multiplexed 9-Cycle Data Memory CE0-3 Write ...
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ELECTRICAL CHARACTERISTICS—(NONMULTIPLEXED ADDRESS/DATA BUS) (Note 13) PARAMETER Oscillator Frequency PSEN Pulse Width PSEN Low to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN Port 1 Address, Port Valid Instruction In Port 2, ...
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MOVX CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS) PARAMETER RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold After Read Data Float After Read Port 1 Address, Port 4 CE, Port 5 PCE to Valid Data In Port ...
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Figure 14. Nonmultiplexed 9-Cycle Address/Data CE0-3 MOVX Read/Write Operation ...
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Figure 15. Nonmultiplexed 9-Cycle Address/Data PCE0-3 MOVX Read/Write Operation ...
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Figure 16. Nonmultiplexed 2-Cycle Data Memory Figure 17. Nonmultiplexed 2-Cycle Data Memory CE0-3 Read PCE0 - 3 Read or Write ...
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Figure 18. Nonmultiplexed 2-Cycle Data Memory CE0-3 Write Figure 19. Nonmultiplexed 3-Cycle Data Memory PEC0-3 Read or Write ...
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Figure 20. Nonmultiplexed 3-Cycle Data Memory CE0-3 Read Figure 21. Nonmultiplexed 3-Cycle Data Memory CE0-3 Write ...
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Figure 22. Nonmultiplexed 9-Cycle Data Memory PCE0-3 Read or Write Figure 23. Nonmultiplexed 9-Cycle Data Memory CE0-3 Read ...
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Figure 24. Nonmultiplexed 9-Cycle Data Memory CE0-3 Write t TIME PERIODS MCS SYSTEM CLOCK SELECTION 4X/2X CD1 CD0 EXTERNAL CLOCK CHARACTERISTICS PARAMETER Clock High Time Clock Low Time ...
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SERIAL PORT MODE 0 TIMING CHARACTERISTICS PARAMETER Serial Port Clock Cycle Time Output Data Setup to Clock Rising Output Data Hold from Clock Rising Input Data Hold After Clock Rising Clock Rising Edge to Input Data Valid SYMBOL CONDITIONS SM2 ...
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Figure 26. Serial Port 0 (Synchronous Mode) HIGH-SPEED OPERATION, TXD CLK = XTAL/4 (SM2 = 1) TRADITIONAL 8051 OPERATION, TXD CLOCK = XTAL/12 (SM2 = ...
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POWER-CYCLE TIMING CHARACTERISTICS PARAMETER Crystal Startup Time (Note 14) Power-On Reset Delay (Note 15) Note 14: Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592MHz crystal manufactured by Fox Electronics. Note 15: Reset ...
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PIN DESCRIPTION PIN NAME LQFP PLCC 8, 22, 40, 17, 32, 51 25, 41, 1, 18, 35 RSTOL XTAL2 24 34 ...
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PIN DESCRIPTION (continued) PIN NAME LQFP PLCC 58–64, 1 2–8, 10 P1.0–P1 (P2. (P2. A10 (P2.2) ...
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... CAN interface peripheral enable signals. Setting the SP1EC bit will relocate the RXD1 and TXD1 functions to P5.3-P5.2 as described in the High-Speed Microcontroller User’s Guide: DS80C390 Supplement. The reset condition of Port 1 is all bits at logic 1 via a weak pullup. The logic 1 state also serves as an input mode, since external circuits writing to the port can overdrive the weak pullup ...
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... Figure 28. Block Diagram DS80C390 ...
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... All of the standard 8051 resources such as three timer/counters, serial port, and four 8-bit I/O ports (plus two 8-bit ports dedicated to memory interfacing) are included in the DS80C390. In addition it includes a second hardware serial port, seven additional interrupts, programmable watchdog timer, brownout monitor, power-fail reset, and a programmable output clock that supports an IrDA interface ...
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... A, @DPTR” instruction and the “MOV direct, direct” instruction required the same amount of time: two machine cycles or 24 oscillator cycles. In the DS80C390, the MOVX instruction takes as little as two machine cycles, or eight oscillator cycles, but the “MOV direct, direct” uses three machine cycles oscillator cycles ...
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Table 1. SFR Locations REGISTER BIT7 BIT6 P4 P4.7 P4.6 SP DPL DPH DPL1 DPH1 DPS ID1 ID0 PCON SMOD_0 SMOD0 TCON TF1 TR1 TMOD GATE C/T TL0 TL1 TH0 TH1 CKCON WD1 WD0 P1 INT5/P1.7 INT4/P1.6 INT3/P1.5 INT2/P1.4 TXD1/P1.3 ...
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Table 1. SFR Locations (continued) REGISTER BIT7 BIT6 C0M14C MSRDY ETI C0M15C MSRDY ETI SCON1 SM0/FE_1 SM1_1 SBUF1 PMR CD1 CD0 STATUS PIP HIP MCON IDM1 IDM0 TA T2CON TF2 EXF2 T2MOD — — RCAP2L RCAP2H TL2 TH2 COR IRDACK ...
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ON-CHIP ARITHMETIC ACCELERATOR An on-chip math accelerator allows the microcontroller to perform 32-bit and 16-bit multiplication, division, shifting, and normalization using dedicated hardware. Math operations are performed by sequentially loading three special registers. The mathematical operation is determined by the ...
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... C register (MC;D5h), LSB first. The 40-bit accumulator can be read by performing five reads of the multiplier C register, MSB first. MEMORY ADDRESSING The DS80C390 incorporates three internal memory areas: 256 bytes of scratchpad (or direct) RAM 4kB of SRAM configurable as various combinations of MOVX data memory, stack memory, and MOVC program memory 512 bytes of RAM reserved for the CAN message centers ...
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... MOVX data memory is reserved for use by the 10-bit expanded stack. Internal memory accesses will not generate WR, RD, or PSEN strobes. The DS80C390 can configure its 4kB of internal SRAM as combined program and data memory. This allows the application software to execute self-modifiable code. The technique loads the 4kB SRAM with bootstrap loader software, and then modifies the IDM1 and IDM0 bits to map the 4kB starting at memory location 40000h ...
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... STRETCH MEMORY CYCLES The DS80C390 allows user-application software to select the number of machine cycles it takes to execute a MOVX instruction, allowing access to both fast and slow off-chip data memory and/or peripherals without glue logic. High-speed systems often include memory-mapped peripherals such as LCDs or UARTs with slow access times may not be necessary or desirable to access external devices at full speed ...
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... INC DPS instruction without disturbing other bits in the DPS register. Unlike the standard 8051, the DS80C390 has the ability to decrement as well as increment the data pointers without additional instructions. When the INC DPTR instruction is executed, the active DPTR increments or decrements according to the ID1, ID0 (DPS ...
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... INC DPTR CLOCK CONTROL AND POWER MANAGEMENT The DS80C390 includes a number of unique features that allow flexibility in selecting system clock sources and operating frequencies. To support the use of inexpensive crystals while allowing full speed operation, a clock multiplier is included in the processor’s clock circuit. Also, in addition to the standard 80C32 idle and power-down (Stop) modes, the DS80C390 provides a new power management mode ...
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... This means that the maximum crystal oscillator or external clock source is 10MHz when using the 4X setting, and 20MHz when using the 2X setting. The primary advantage of the clock multiplier is that it allows the microcontroller to use slower crystals to achieve the same performance level ...
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POWER MANAGEMENT MODE (PMM) AND SWITCHBACK Power consumption in PMM is less than in idle mode, and approximately one quarter of that consumed in divide- by-four mode. While PMM and Idle modes leave the power-hungry internal timers running, PMM runs ...
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... BANDGAP SELECT The DS80C390 provides two enhancements to stop mode. As described below, the device provides a band-gap reference to determine power-fail interrupt and reset thresholds. The bandgap select bit, BGS (RCON.0), controls the bandgap reference. Setting BGS to 1 keeps the bandgap reference enabled during stop mode. The default or reset condition of the bit is logic 0, which disables the bandgap during stop mode ...
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... The default state of ALEOFF ALE normally toggles at a frequency of XTAL/4. PERIPHERAL OVERVIEW The DS80C390 provides several of the most commonly needed peripheral functions in microcomputer-based systems. New functions include a second serial port, power-fail reset, power-fail interrupt flag, and a programmable watchdog timer. In addition, the microcontroller contains two CAN modules for industrial communication applications. Each of these peripherals is described in the following paragraphs. More details are available in the High-Speed Microcontroller User’ ...
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... The SCON0 register provides control for serial port 0 while its I/O buffer is SBUF0. The registers SCON1 and SBUF1 provide the same functions for the second serial port. A full description of the use and operation of both serial ports can be found in the High-Speed Microcontroller User’s Guide: DS80C390 Supplement. WATCHDOG TIMER The watchdog is a free-running, programmable timer that can set a flag, cause an interrupt, and/or reset the microcontroller if allowed to reach a preselected timeout ...
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... The flag is independent of the interrupt enable and must be cleared by software. EXTERNAL RESET PINS The DS80C390 has reset input (RST) and reset output (RSTOL) pins. The RSTOL pin supplies an active-low reset when the microprocessor is issued a reset from either a high on the RST pin, a timeout of the watchdog timer, a crystal oscillator fail internally detected power fail ...
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... CONTROLLER AREA NETWORK (CAN) MODULE The DS80C390 incorporates two CAN controllers that are fully compliant with the CAN 2.0B specification. CAN is a highly robust, high-performance communication protocol for serial communications. Popular in a wide range of applications including automotive, medical, heating, ventilation, and industrial control, the CAN architecture allows for the construction of sophisticated networks with a minimum of external hardware ...
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... Note that setting the CMA bit employs a special 23rd address bit that is only used for addressing CAN MOVX memory. The DS80C390’s internal architecture requires that the device be in one of the two 22-bit addressing modes when the CMA bit is set to correctly use the 23rd bit and access the CAN MOVX memory ...
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MOVX MESSAGE CENTERS FOR CAN 0 REGISTER 7 6 C0MID0 MID07 MID06 C0MA0 M0AA7 M0AA6 C0MID1 MID17 MID16 C0MA1 M1AA7 M1AA6 C0BT0 SJW1 SJW0 C0BT1 SMP TSEG26 C0SGM0 ID28 ID27 C0SGM1 ID20 ID19 C0EGM0 ID28 ID27 C0EGM1 ID20 ID19 C0EGM2 ...
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MOVX MESSAGE CENTERS FOR CAN 1 REGISTER 7 6 C1MID0 MID07 MID06 C1MA0 M0AA7 M0AA6 C1MID1 MID17 MID16 C1MA1 M1AA7 M1AA6 C1BT0 SJW1 SJW0 C1BT1 SMP TSEG26 C1SGM0 ID28 ID27 C1SGM1 ID20 ID19 C1EGM0 ID28 ID27 C1EGM1 ID20 ID19 C1EGM2 ...
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... Note that message center 15 can only be used in a receive mode. To avoid a priority inversion, the DS80C390 CAN processors are configured to reload the transmit buffer with the message of the highest priority (lowest message center number) whenever an arbitration is lost or an error condition occurs. ...
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Table 14. Arbitration/Masking Feature Summary ARBITRATION TEST NAME REGISTERS Message Center Standard 11-Bit Arbitration Registers 0–1 Arbitration (CAN (Located in each 2.0A) Message Center, MOVX memory) Message Center Extended 29-Bit Arbitration Registers 0–3 Arbitration (CAN (Located in each 2.0B) Message ...
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MESSAGE BUFFERING/OVERWRITE If a message center is configured for reception (T and the previous message has not been read (DTUP = 1), then the disposition of an incoming message to that message center is controlled by the WTOE ...
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... PACKAGE INFORMATION For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE 68 PLCC 64 LQFP PACKAGE CODE Q68-1 C64L DOCUMENT NO. 21-0049 21-0083 ...
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... The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corp. DS80C390 Dual CAN High-Speed Microprocessor DESCRIPTION time period table ...